[PDF][PDF] High throughput FPGA Implementation of Data Encryption Standard with time variable sub-keys

S Oukili, S Bri - International Journal of Electrical and Computer …, 2016 - academia.edu
The Data Encryption Standard (DES) was the first modern and the most popular symmetric
key algorithm used for encryption and decryption of digital data. Even though it is nowadays …

Finding the best FPGA implementation of the DES algorithm to secure smart cards

K Dichou, V Tourtchine… - 2015 4th International …, 2015 - ieeexplore.ieee.org
Smart cards are often used in different applications which require strong security protection
and authentication; such as corporate organization, government, banks etc. its popularity is …

FPGA implementation of Data Encryption Standard using time variable permutations

S Oukili, S Bri - 2015 27th International Conference on …, 2015 - ieeexplore.ieee.org
The Data Encryption Standard (DES) was the first modern and the most popular symmetric
key algorithm used for encryption and decryption of digital data. Even though it is nowadays …

Implementation of DES using pipelining concept with skew core key scheduling in secure transmission of images

K Praveen, P Poornachandran, ASR Ajai - Proceedings of the second …, 2012 - dl.acm.org
Digital image processing is a very expanding area with applications reaching out into
various fields such as defence, medicine, space exploration, authentication, automated …

[PDF][PDF] Fpga implementation of the pipelined data encryption standard (des) based on variable time data permutation

KMA Abd El-Latif, HFA Hamed… - the online journal on …, 2010 - Citeseer
This paper describes a high-performance reconfigurable hardware implementation of the
new Data Encryption Standard (DES) based on variable time data permutation. The …

Effective implementation of DES algorithm for voice scrambling

JE John, AS Remya Ajai, P Poornachandran - Recent Trends in Computer …, 2012 - Springer
This paper presents a high performance reconfigurable hardware implementation of speech
scrambling–descrambling system which can be used for military and high security …

[PDF][PDF] Multi-Layered Cryptographic Processor for Network Security

P Lata, V Anitha - International Journal of Scientific and Research …, 2012 - Citeseer
This paper presents a multi-layered architecture for the security of network and data using a
layered structure of cryptographic algorithms. This architecture gives benefit of low area and …

Hardware design of cryptographic accelerator

M Hulič, L Vokorokos, N Ádám… - 2018 IEEE 16th World …, 2018 - ieeexplore.ieee.org
The goal of this paper is representation of computing unit focused on implementation
hardware cryptography accelerator. After analysis of assigned problem, there are next …

[PDF][PDF] Biomedical Image Transmission Based on Modified Feistal Algorithm

JE John - International Journal of Computer Science & …, 2013 - academia.edu
This paper presents a reconfigurable, high performance hardware implementation of highly
secure biomedical image transmission system which can be used for sending medical …

[PDF][PDF] Pipelining concept for low power DES implementation

A Eshack, S Krishnakumar - International Journal of Computer …, 2016 - academia.edu
An implementation of Data Encryption Standard (DES), one of the most widely accepted
cryptographic standards, using the pipelining concept is described in the paper. Pipelining is …