[HTML][HTML] Reliability of analog resistive switching memory for neuromorphic computing
As artificial intelligence calls for novel energy-efficient hardware, neuromorphic computing
systems based on analog resistive switching memory (RSM) devices have drawn great …
systems based on analog resistive switching memory (RSM) devices have drawn great …
The challenges and emerging technologies for low-power artificial intelligence IoT systems
L Ye, Z Wang, Y Liu, P Chen, H Li… - … on Circuits and …, 2021 - ieeexplore.ieee.org
The Internet of Things (IoT) is an interface with the physical world that usually operates in
random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips …
random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips …
In situ learning using intrinsic memristor variability via Markov chain Monte Carlo sampling
Resistive memory technologies could be used to create intelligent systems that learn locally
at the edge. However, current approaches typically use learning algorithms that cannot be …
at the edge. However, current approaches typically use learning algorithms that cannot be …
[HTML][HTML] Tuning oxygen vacancies and resistive switching properties in ultra-thin HfO2 RRAM via TiN bottom electrode and interface engineering
Resistive random access memory (RRAM) technologies based on non-volatile resistive
filament redox switching oxides have the potential of drastically improving the performance …
filament redox switching oxides have the potential of drastically improving the performance …
Timely: Pushing data movements and interfaces in pim accelerators towards local and in time domain
Resistive-random-access-memory (ReRAM) based processing-in-memory (R2PIM)
accelerators show promise in bridging the gap between Internet of Thing devices' …
accelerators show promise in bridging the gap between Internet of Thing devices' …
High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon
In-memory computing can be used to overcome the von Neumann bottleneck—the need to
shuffle data between separate memory and computational units—and help improve …
shuffle data between separate memory and computational units—and help improve …
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W edge AI accelerator with 2-MByte on-chip foundry resistive RAM for efficient training and inference
Implementing edge artificial intelligence (AI) inference and training is challenging with
current memory technologies. As deep neural networks (DNNs) grow in size, this problem is …
current memory technologies. As deep neural networks (DNNs) grow in size, this problem is …
Device‐Algorithm Co‐Optimization for an On‐Chip Trainable Capacitor‐Based Synaptic Device with IGZO TFT and Retention‐Centric Tiki‐Taka Algorithm
Analog in‐memory computing synaptic devices are widely studied for efficient
implementation of deep learning. However, synaptic devices based on resistive memory …
implementation of deep learning. However, synaptic devices based on resistive memory …
RADAR: A fast and energy-efficient programming technique for multiple bits-per-cell RRAM arrays
HfO 2-based resistive RAM (RRAM) is an emerging nonvolatile memory technology that has
recently been shown capable of storing multiple bits-per-cell. The energy/delay costs of an …
recently been shown capable of storing multiple bits-per-cell. The energy/delay costs of an …
Sparse attention acceleration with synergistic in-memory pruning and on-chip recomputation
A Yazdanbakhsh, A Moradifirouzabadi… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
As its core computation, a self-attention mechanism gauges pairwise correlations across the
entire input sequence. Despite favorable performance, calculating pairwise correlations is …
entire input sequence. Despite favorable performance, calculating pairwise correlations is …