Low-power SAR ADC design: Overview and survey of state-of-the-art techniques
This paper presents an overview for low-power successive approximation register (SAR)
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
Challenges and opportunities toward fully automated analog layout design
Realizing the layouts of analog/mixed-signal (AMS) integrated circuits (ICs) is a complicated
task due to the high design flexibility and sensitive circuit performance. Compared with the …
task due to the high design flexibility and sensitive circuit performance. Compared with the …
A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation
As any analog-to-digital converter (ADC) with a front-end sample-and-hold (S/H) circuit,
successive approximation register (SAR) ADC suffers from a fundamental signal-to-noise …
successive approximation register (SAR) ADC suffers from a fundamental signal-to-noise …
A 0.5–1.1-V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator
A successive approximation register (SAR) analog-to-digital converter (ADC) with a voltage-
controlled oscillator (VCO)-based comparator is presented in this paper. The relationship …
controlled oscillator (VCO)-based comparator is presented in this paper. The relationship …
16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation
As with any ADC with a front-end S/H, the SAR ADC suffers from a fundamental SNR
challenge: its sampling kT/C noise. To satisfy the SNR requirement, the input capacitor has …
challenge: its sampling kT/C noise. To satisfy the SNR requirement, the input capacitor has …
A 14-bit 4-MS/s VCO-based SAR ADC with deep metastability facilitated mismatch calibration
This article presents a 14-bit 4-MS/s voltage-controlled oscillator (VCO)-based successive
approximation register (SAR) analog-to-digital converter (ADC), where the metastability of …
approximation register (SAR) analog-to-digital converter (ADC), where the metastability of …
A Low-offset VCO-based time-domain comparator using a phase frequency detector with reduced dead and blind Zones
M Esmaeilzadeh, Y Audet, M Ali… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
We present in this paper a high-precision voltage-controlled oscillators (VCO)-based time-
domain (TD) comparator. It involves two identical and linear VCOs to convert the input …
domain (TD) comparator. It involves two identical and linear VCOs to convert the input …
A 12-bit 20-kS/s 640-nW SAR ADC with a VCDL-based open-loop time-domain comparator
This brief presents a 12-bit ultra-low-power asynchronous successive approximation register
(SAR) analog-to-digital converter (ADC). A voltage-controlled delay line (VCDL) based open …
(SAR) analog-to-digital converter (ADC). A voltage-controlled delay line (VCDL) based open …
VCO-based comparator: A fully adaptive noise scaling comparator for high-precision and low-power SAR ADCs
K Yoshioka - IEEE Transactions on Very Large Scale …, 2021 - ieeexplore.ieee.org
A voltage-controlled oscillator (VCO)-based comparator that automatically adapts its noise
performance reflecting the input voltage difference () is presented. Such adaptive operation …
performance reflecting the input voltage difference () is presented. Such adaptive operation …
A two-step ADC with a continuous-time SAR-based first stage
This article presents a two-step analog-to-digital converter (ADC) that operates its first-stage
successive approximation register (SAR) ADC in the continuous-time (CT) domain. It avoids …
successive approximation register (SAR) ADC in the continuous-time (CT) domain. It avoids …