Leakage aware dynamic voltage scaling for real-time embedded systems

R Jejurikar, C Pereira, R Gupta - Proceedings of the 41st annual Design …, 2004 - dl.acm.org
A five-fold increase in leakage current is predicted with each technology generation. While
Dynamic Voltage Scaling (DVS) is known to reduce dynamic power consumption, it also …

Computer architecture: Challenges and opportunities for the next decade

T Agerwala, S Chatterjee - IEEE Micro, 2005 - ieeexplore.ieee.org
Computer architecture forms the bridge between application needs and the capabilities of
the underlying technologies. As application demands change and technologies cross …

IATAC: a smart predictor to turn-off L2 cache lines

J Abella, A González, X Vera, MFP O'Boyle - ACM Transactions on …, 2005 - dl.acm.org
As technology evolves, power dissipation increases and cooling systems become more
complex and expensive. There are two main sources of power dissipation in a processor …

Dynamic memory architecture employing passive expiration of data

PG Emma, RK Montoye, WR Reohr - US Patent 8,020,073, 2011 - Google Patents
Apparatus for passively tracking expired data in a dynamic memory includes a time stamp
memory configurable for storing information relating to a refresh status of one or more …

Dynamic memory architecture employing passive expiration of data

PG Emma, RK Montoye, WR Reohr - US Patent 7,290,203, 2007 - Google Patents
In accordance With the aforementioned need, the present invention, in an illustrative
embodiment, is an improved dynamic memory architecture that utiliZes a unique passive …

Low power processor architectures and contemporary techniques for power optimization–a review

MY Qadri, HS Gujarathi… - Journal of …, 2009 - repository.essex.ac.uk
The technological evolution has increased the number of transistors for a given die area
significantly and increased the switching speed from few MHz to GHz range. Such inversely …

Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache

J Li, L Shi, CJ Xue, C Yang, Y Xu - 2011 9th IEEE Symposium …, 2011 - ieeexplore.ieee.org
Hybrid cache architectures have been proposed to mitigate the increasing on-chip power
dissipation through the exploitation of the emerging non-volatile memories (NVMs). To …

Location cache: a low-power L2 cache system

R Min, WB Jone, Y Hu - … of the 2004 international symposium on Low …, 2004 - dl.acm.org
While set-associative caches incur fewer misses than direct-mapped caches, they typically
have slower hit times and higher power consumption, when multiple tag and data banks are …

Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh

J Li, L Shi, Q Li, CJ Xue, Y Chen, Y Xu… - ACM Transactions on …, 2013 - dl.acm.org
Spin-Torque Transfer RAM (STT-RAM) is a promising candidate for SRAM replacement
because of its excellent features, such as fast read access, high density, low leakage power …

Exploring the limits of leakage power reduction in caches

Y Meng, T Sherwood, R Kastner - ACM Transactions on Architecture and …, 2005 - dl.acm.org
If current technology scaling trends hold, leakage power dissipation will soon become the
dominant source of power consumption. Caches, because of the fact that they account for …