Physically unclonable functions using two-level finite state machine

V Vijay, K Chaitanya, CS Pittala… - Journal of VLSI …, 2022 - vlsijournal.com
The usage of physically unclonable functions is for authentications, identification
applications, signature generation, IC metering, and cryptographic key generation …

6Transistor SRAM cell designed using 18nm FinFET technology

RR Vallabhuni, P Shruthi, G Kavya… - 2020 3rd International …, 2020 - ieeexplore.ieee.org
The electronics devices are facing a foremost drawback of standby leakage, which will
severely impact the electronics industry from the past few decades. As well as the need for …

Universal shift register designed at low supply voltages in 20 nm FinFET using multiplexer

RR Vallabhuni, J Sravana, CS Pittala, M Divya… - … Systems: Proceedings of …, 2021 - Springer
Shift registers are utilized in personal computer systems as an element of ability, including
RAM and numerous types of registers. Besides, automatic framework tasks including …

Design of unbalanced ternary logic gates and arithmetic circuits

V Vijay, CS Pittala, KC Koteshwaramma… - Journal of VLSI …, 2022 - vlsijournal.com
The design of ternary Logic gates–Ternary NAND, Ternary NOR and Standard Ternary
Inverter based on the 18nm FinFET technology is proposed. The Ternary logic systems …

Novel methodology to validate DUTs using single access structure

CS Pittala, J Sravana, G Ajitha, P Saritha… - … Engineering & Nano …, 2021 - ieeexplore.ieee.org
Conventional shift-based scan chains have the drawback of peak power consumption which
is reduced by the proposed single cycle access test structure for logic test. With the reduction …

Energy Efficient Decoder Circuit Using Source Biasing Technique in CNTFET Technology

CS Pittala, M Lavanya, V Vijay, Y Reddy… - 2021 Devices for …, 2021 - ieeexplore.ieee.org
VLSI technology is essential for chip fabrication, and 3 to 8 decoder circuits are used in
electronic gadgets; consistency of design, small, fast, in this proposed circuit, 3 to 8 decoder …

Adaptive and recursive vedic karatsuba multiplier using non linear carry select adder

M Saritha, K Chaitanya, V Vijay… - Journal of VLSI …, 2022 - vlsijournal.com
Adaptive And Recursive Vedic Karatsuba Multiplier Using Non Linear Carry Select Adder Page 1
Journal of VLSI circuits and systems, , ISSN 2582-1458 22 RESEARCH ARTICLE …

Fake currency recognition system using edge detection

PA Babu, P Sridhar… - … Research in Technology …, 2022 - ieeexplore.ieee.org
In this paper, we propose a system for currency recognition system and the detection of fake
Indian currency banknotes using image processing techniques. It is hard for people to …

All-digital phase locked loop (ADPLL) topologies for RFID system application: A review

SN Ishak, J Sampe, Z Yusoff, M Faseehuddin - Jurnal Teknologi, 2022 - journals.utm.my
An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver
application such as radio-frequency identification (RFID) system has gained popularity by …

Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer

J Sravana, KS Indrani, M Saranya, PS Kiran… - Journal of VLSI …, 2022 - vlsijournal.com
This paper demonstrates the improved adaptation of the Vedic Multiplier using the Vedic
standards, which includes old sutras. In this paper, current and proposed model are …