[HTML][HTML] A survey on security analysis of machine learning-oriented hardware and software intellectual property

A Tauhid, L Xu, M Rahman, E Tomai - High-Confidence Computing, 2023 - Elsevier
Intellectual Property (IP) includes ideas, innovations, methodologies, works of authorship
(viz., literary and artistic works), emblems, brands, images, etc. This property is intangible …

Provably secure camouflaging strategy for IC protection

M Li, K Shamsi, T Meade, Z Zhao, B Yu… - IEEE transactions on …, 2017 - ieeexplore.ieee.org
The advancing of reverse engineering techniques has complicated the efforts in intellectual
property protection. Proactive methods have been developed recently, among which layout …

Reverse engineering camouflaged sequential circuits without scan access

M El Massad, S Garg… - 2017 IEEE/ACM …, 2017 - ieeexplore.ieee.org
Integrated circuit (IC) camouflaging is a promising technique to protect the design of a chip
from reverse engineering. However, recent work has shown that even camouflaged ICs can …

Robust design-for-security architecture for enabling trust in IC manufacturing and test

U Guin, Z Zhou, A Singh - … on Very Large Scale Integration (VLSI …, 2018 - ieeexplore.ieee.org
Due to the prohibitive costs of semiconductor manufacturing, most system-on-chip design
companies outsource their production to offshore foundries. As most of these devices are …

Physical design obfuscation of hardware: A comprehensive investigation of device and logic-level techniques

A Vijayakumar, VC Patil, DE Holcomb… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
The threat of hardware reverse engineering is a growing concern for a large number of
applications. A main defense strategy against reverse engineering is hardware obfuscation …

CamoPerturb: Secure IC camouflaging for minterm protection

M Yasin, B Mazumdar, O Sinanoglu… - 2016 IEEE/ACM …, 2016 - ieeexplore.ieee.org
Integrated circuit (IC) camouflaging is a layout-level technique that thwarts reverse
engineering attacks on ICs by introducing camouflaged cells that look alike, but can …

Incremental SAT-based reverse engineering of camouflaged logic circuits

C Yu, X Zhang, D Liu, M Ciesielski… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Layout-level gate or routing camouflaging techniques have attracted interest as
countermeasures against reverse engineering of combinational logic. In order to minimize …

Logic locking: A survey of proposed methods and evaluation metrics

S Dupuis, ML Flottes - Journal of Electronic Testing, 2019 - Springer
The outsourcing business model is dominating the semiconductor industry. Due to this loss
of control over the design flow, several threats have become a major source of concern …

Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging

S Patnaik, M Ashraf, O Sinanoglu… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Layout camouflaging can protect the intellectual property of modern circuits. Most prior art,
however, incurs excessive layout overheads and necessitates customization of active …

Logic locking for secure outsourced chip fabrication: A new attack and provably secure defense mechanism

ME Massad, J Zhang, S Garg… - arXiv preprint arXiv …, 2017 - arxiv.org
Chip designers outsource chip fabrication to external foundries, but at the risk of IP theft.
Logic locking, a promising solution to mitigate this threat, adds extra logic gates (key gates) …