An overview of capacity results for synchronization channels
M Cheraghchi, J Ribeiro - IEEE Transactions on Information …, 2020 - ieeexplore.ieee.org
Synchronization channels, such as the well-known deletion channel, are surprisingly harder
to analyze than memoryless channels, and they are a source of many fundamental problems …
to analyze than memoryless channels, and they are a source of many fundamental problems …
Magnetic racetrack memory: From physics to the cusp of applications within a decade
Racetrack memory (RTM) is a novel spintronic memory-storage technology that has the
potential to overcome fundamental constraints of existing memory and storage devices. It is …
potential to overcome fundamental constraints of existing memory and storage devices. It is …
Levenshtein's reconstruction problem with different error patterns
V Junnila, T Laihonen, T Lehtilä - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
In this paper, we consider Levenshtein's sequence reconstruction problem in which the
same codeword is transmitted through N channels each introducing a different set of errors …
same codeword is transmitted through N channels each introducing a different set of errors …
Correcting multiple deletions and insertions in racetrack memory
Racetrack memory is a tape-like structure where data is stored sequentially as a track of
single-bit memory cells. The cells are accessed through read/write ports, called heads …
single-bit memory cells. The cells are accessed through read/write ports, called heads …
Correcting deletions in multiple-heads racetrack memories
One of the main challenges in developing racetrack memory systems is the limited precision
in controlling the track shifts, that in turn affects the reliability of reading and writing the data …
in controlling the track shifts, that in turn affects the reliability of reading and writing the data …
Constant L1-weight codes under L∞-metric
This paper studies the construction of constant-weight codes under-metric, which could be
used to design codes addressing 0-indels (ie, the insertion/deletion of 0's only). Based on …
used to design codes addressing 0-indels (ie, the insertion/deletion of 0's only). Based on …
Blendcache: An energy and area efficient racetrack last-level-cache architecture
F Hameed, J Castrillon - IEEE Transactions on Computer-Aided …, 2022 - ieeexplore.ieee.org
Racetrack memory (RTM) is a promising nonvolatile memory that provides multibit storage
cells achieving a higher area and leakage energy efficiency compared to contemporary …
cells achieving a higher area and leakage energy efficiency compared to contemporary …
Codes for constrained periodicity
Reliability is an inherent challenge for the emerging nonvolatile technology of racetrack
memories, and there exists a fundamental relationship between codes designed for …
memories, and there exists a fundamental relationship between codes designed for …
On Unique Error Patterns in the Levenshtein's Sequence Reconstruction Model
V Junnila, T Laihonen, T Lehtilä - arXiv preprint arXiv:2406.14125, 2024 - arxiv.org
In the Levenshtein's sequence reconstruction problem a codeword is transmitted through $
N $ channels and in each channel a set of errors is introduced to the transmitted word. In …
N $ channels and in each channel a set of errors is introduced to the transmitted word. In …
[图书][B] Correcting Errors in DNA Storage
J Sima - 2022 - search.proquest.com
DNA-based storage has potentially unprecedented advantages of high information density
and long duration, and is one of the promising techniques to meet the ever-growing …
and long duration, and is one of the promising techniques to meet the ever-growing …