Model-based exploration of the design space for heterogeneous systems on chip

H Blume, H Hubert, HT Feldkamper… - … on Application-Specific …, 2002 - ieeexplore.ieee.org
The exploration of the design space for heterogeneous reconfigurable systems on chip
(SoC) becomes more and more important. As modern SoCs include a variety of different …

Ambient intelligence: gigascale dreams and nanoscale realities

H De Man - ISSCC. 2005 IEEE International Digest of Technical …, 2005 - ieeexplore.ieee.org
Ambient intelligence (AmI) is a vision of a world in which people will be surrounded by
networks of intelligent devices that are sensitive and adaptive to their needs. This concept …

[图书][B] Ultra-low energy domain-specific instruction-set processors

F Catthoor, P Raghavan, A Lambrechts, M Jayapala… - 2010 - books.google.com
Modern consumers carry many electronic devices, like a mobile phone, digital camera, GPS,
PDA and an MP3 player. The functionality of each of these devices has gone through an …

Implementation of scalable power and area efficient high-throughput Viterbi decoders

T Gemmeke, M Gansen, TG Noll - IEEE Journal of Solid-State …, 2002 - ieeexplore.ieee.org
Today's data reconstruction in digital communication systems requires designs of highest
throughput rate at low power. The Viterbi algorithm is a key element in such digital signal …

A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques

N Reynders, W Dehaene - IEEE Asian Solid-State Circuits …, 2011 - ieeexplore.ieee.org
This paper presents a pipelined 32 bit sub-threshold adder in a 90nm CMOS technology that
combines MHz-performance with sub-pJ energy consumption. To increase variation …

Design flow for embedded FPGAs based on a flexible architecture template

B Neumann, T von Sydow, H Blume… - Proceedings of the …, 2008 - dl.acm.org
Modern digital signal processing applications have an increasing demand for computational
power while needing to preserve low power dissipation and high flexibility. For many …

Quantitative analysis of embedded FPGA-architectures for arithmetic

T von Sydow, B Neumann, H Blume… - IEEE 17th International …, 2006 - ieeexplore.ieee.org
Embedding FPGAs (eFPGAs) in modern SoCs provides a high amount of flexibility while
high-throughput digital signal processing algorithms can be realised efficiently. An analysis …

Design and implementation of a field programmable CRC circuit architecture

C Toal, K McLaughlin, S Sezer… - IEEE transactions on very …, 2009 - ieeexplore.ieee.org
The design and implementation of a programmable cyclic redundancy check (CRC)
computation circuit architecture, suitable for deployment in network related system-on-chips …

27.3 A 210mV 5MHz variation-resilient near-threshold JPEG encoder in 40nm CMOS

N Reynders, W Dehaene - 2014 IEEE International Solid-State …, 2014 - ieeexplore.ieee.org
Operating circuits in the near-threshold region enables large energy savings. However, such
circuits also pose many challenges, such as increased delay, unwanted leakage paths and …

Design optimization of low-power high-performance DSP building blocks

T Gemmeke, M Gansen… - IEEE Journal of Solid …, 2004 - ieeexplore.ieee.org
In recent years, power dissipation along with silicon area has become the key figure in chip
design. The increasing demands on system performance require high-performance digital …