S Mittal - ACM Journal on Emerging Technologies in Computing …, 2016 - dl.acm.org
Recent trends of increasing core-count and bandwidth/memory wall have motivated researchers to explore novel memory technologies for designing processor components …
Increasing single-cell DRAM error rates have pushed DRAM manufacturers to adopt on-die error-correction coding (ECC), which operates entirely within a DRAM chip to improve …
Racetrack memory is a new technology, which utilizes magnetic domains along a nanoscopic wire in order to obtain extremely high storage density. In racetrack memory …
Experimental characterization of DRAM errors is a powerful technique for understanding DRAM behavior and provides valuable insights for improving overall system performance …
Racetrack memories (RTMs) have drawn considerable attention from computer architects of late. Owing to the ultra-high capacity and comparable access latency to SRAM, RTMs are …
G Wang, Y Zhang, B Zhang, B Wu, J Nan… - … on Circuits and …, 2018 - ieeexplore.ieee.org
Information storage and transfer via current-induced domain wall (DW) motions exhibit significant density-speed-energy advantages, which inspires numerous emerging devices …
The growth in data needs of modern applications has created significant challenges for modern systems leading to a “memory wall.” Spintronic Domain-Wall Memory (DWM) …
K Roxy, S Ollivier, A Hoque… - IEEE Transactions …, 2020 - ieeexplore.ieee.org
Domain-wall memory (DWM), an extension to spin transfer torque-magnetic random access memory (STT-MRAM), stores multiple bits, each bit in an individual domain within a …
Racetrack memory is a promising new non-volatile memory technology, especially because of the density of its 3D implementation. However, for 3D racetrack to reach its potential …