Magnetic racetrack memory: From physics to the cusp of applications within a decade

R Bläsing, AA Khan, PC Filippou, C Garg… - Proceedings of the …, 2020 - ieeexplore.ieee.org
Racetrack memory (RTM) is a novel spintronic memory-storage technology that has the
potential to overcome fundamental constraints of existing memory and storage devices. It is …

A survey of techniques for architecting processor components using domain-wall memory

S Mittal - ACM Journal on Emerging Technologies in Computing …, 2016 - dl.acm.org
Recent trends of increasing core-count and bandwidth/memory wall have motivated
researchers to explore novel memory technologies for designing processor components …

Bit-exact ECC recovery (BEER): Determining DRAM on-die ECC functions by exploiting DRAM data retention characteristics

M Patel, JS Kim, T Shahroodi… - 2020 53rd Annual …, 2020 - ieeexplore.ieee.org
Increasing single-cell DRAM error rates have pushed DRAM manufacturers to adopt on-die
error-correction coding (ECC), which operates entirely within a DRAM chip to improve …

Coding for racetrack memories

YM Chee, HM Kiah, A Vardy… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Racetrack memory is a new technology, which utilizes magnetic domains along a
nanoscopic wire in order to obtain extremely high storage density. In racetrack memory …

Understanding and modeling on-die error correction in modern DRAM: An experimental study using real devices

M Patel, JS Kim, H Hassan… - 2019 49th Annual IEEE …, 2019 - ieeexplore.ieee.org
Experimental characterization of DRAM errors is a powerful technique for understanding
DRAM behavior and provides valuable insights for improving overall system performance …

RTSim: A cycle-accurate simulator for racetrack memories

AA Khan, F Hameed, R Bläsing… - IEEE Computer …, 2019 - ieeexplore.ieee.org
Racetrack memories (RTMs) have drawn considerable attention from computer architects of
late. Owing to the ultra-high capacity and comparable access latency to SRAM, RTMs are …

Ultra-dense ring-shaped racetrack memory cache design

G Wang, Y Zhang, B Zhang, B Wu, J Nan… - … on Circuits and …, 2018 - ieeexplore.ieee.org
Information storage and transfer via current-induced domain wall (DW) motions exhibit
significant density-speed-energy advantages, which inspires numerous emerging devices …

CORUSCANT: Fast efficient processing-in-racetrack memories

S Ollivier, S Longofono, P Dutta, J Hu… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
The growth in data needs of modern applications has created significant challenges for
modern systems leading to a “memory wall.” Spintronic Domain-Wall Memory (DWM) …

A novel transverse read technique for domain-wall “racetrack” memories

K Roxy, S Ollivier, A Hoque… - IEEE Transactions …, 2020 - ieeexplore.ieee.org
Domain-wall memory (DWM), an extension to spin transfer torque-magnetic random access
memory (STT-MRAM), stores multiple bits, each bit in an individual domain within a …

Foosball coding: Correcting shift errors and bit flip errors in 3D racetrack memory

S Archer, G Mappouras, R Calderbank… - 2020 50th Annual …, 2020 - ieeexplore.ieee.org
Racetrack memory is a promising new non-volatile memory technology, especially because
of the density of its 3D implementation. However, for 3D racetrack to reach its potential …