Technology scaling enables the design of low cost biosignal processing chips suited for
emerging wireless body-area sensing applications. Energy consumption severely limits …

As more and more artificial intelligence capabilities are deployed onto resource-constrained
devices, designers explore several techniques in an effort to boost energy efficiency. Two …

The power-wall problem driven by the stagnation of supply voltages in deep-submicron
technology nodes, is now the major scaling barrier for moving towards the manycore era …

As we move to integration levels of 1,000-core processor chips, it is clear that energy and
power consumption are the most formidable obstacles. To construct such a chip, we need to …

This paper re-addresses standard-cell based SRAM design for sub-threshold operation.
Rather than using flip-flop or latch gates to implement SRAM bitcells, a circuit structure that …

Exploiting a good energy efficiency of standard-cell memory (SCM) and a good area
efficiency of SRAM, a hybrid 2-level on-chip cache structure is first introduced as a …

BACKGROUND For several decades, the processor industry has seen a steady growth in
CPU performance, driven by Moore's Law [1] and Classical (or Dennard) scaling [2]. Under …

High-density electrode arrays used to read out neural activity will soon surpass the limits of
the amount of data that can be transferred within reasonable energy budgets. This is true for …

Emerging and future HealthCare policies are fueling up an application-driven shift toward
long-term monitoring of biosignals by means of embedded ultra-low power Wireless Body …

The power-wall problem caused by the stagnation of supply voltages in deep-submicron
technology nodes, is now the major scaling barrier for towards the manycore era. Although …