A 250 MS/s 2x interleaved 11 bit pipelined SAR ADC in 40 nm digital CMOS is presented.
Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine …

A 12 bit 160 MS/s two-step pipelined SAR ADC was fabricated in a 40 nm CMOS low-
leakage digital process. A background bit-weight calibration exploiting the comparator …

A speed-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error
correction (ADEC) is presented with a straightforward DAC switching algorithm. The …

This paper presents a power-efficient 80 MS/s, 11 bit ENOB ADC. It is realized in 28 nm
CMOS and is based on two interleaved pipelined SAR ADCs. It includes an on-chip …

An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-
digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low …

The successive-approximation (SA) algorithm is traditionally used for low-bandwidth
applications because it requires n clock cycles or more to obtain n-bit resolution. However …

This paper presents the architecture of a 10b 170 MS/s two-step binary-search assisted time-
interleaved SAR ADC. The front-end stage of this ADC is built with a 5b binary-search ADC …

Commonly used 4-level pulse amplitude modulation (PAM-4) scheme limits the amount of
data traffic that can be handled by the PAM-4 based data center interconnects (DCIs) …

The virtual ground reference buffer (VGRB) technique is introduced as a means to improve
the performance of switched-capacitor circuits. The technique enhances the performance by …

A 10-bit pipelined ADC was fabricated using a 65 nm CMOS technology. To reduce power
consumption, switching opamps are used. These switching opamps are designed to have a …