Mitigation of radiation effects in SRAM-based FPGAs for space applications

F Siegle, T Vladimirova, J Ilstad, O Emam - ACM Computing Surveys …, 2015 - dl.acm.org
The use of static random access memory (SRAM)-based field programmable gate arrays
(FPGAs) in harsh radiation environments has grown in recent years. These types of …

FPGA-centric design process for avionic simulation and test

RB Atitallah, V Viswanathan… - … on Aerospace and …, 2017 - ieeexplore.ieee.org
Real-time computing systems are increasingly used in aerospace and avionic industries. In
the face of power challenge, performance requirements and demands for higher flexibility …

Dynamic reconfiguration of modular I/O IP cores for avionic applications

V Viswanathan, B Nakache, RB Atitallah… - 2012 International …, 2012 - ieeexplore.ieee.org
Dynamic reconfiguration using FPGAs has been demonstrated to be highly efficient in
different application domains. However little has been explored in the avionic …

Fast SRAM-FPGA fault injection platform based on dynamic partial reconfiguration

F Ghaffari, F Sahraoui, MEA Benkhelifa… - 2014 26th …, 2014 - ieeexplore.ieee.org
SRAM-based FPGAs are very sensitive to harsh conditions, like radiations or ionizations,
and need to be hardened to insure correct running. To validate any fault tolerant solution for …

Fault detection, isolation and recovery schemes for spaceborne reconfigurable FPGA-based systems

F Siegle - 2016 - figshare.le.ac.uk
This research contributes to a better understanding of how reconfigurable Field
Programmable Gate Array (FPGA) devices can safely be used as part of satellite payload …

Context-aware resources placement for SRAM-based FPGA to minimize checkpoint/recovery overhead

S Fouad, F Ghaffari, MEA Benkhelifa… - … Computing and FPGAs …, 2014 - ieeexplore.ieee.org
Existing SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single
Event Effects (SEE) phenomena in harsh environments. To protect applications running on …

UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAS

C Bernardeschi, L Cassano, A Domenici, L Sterpone - Integration, 2016 - Elsevier
This paper presents UA 2 TPG, a static analysis tool for the untestability proof and automatic
test pattern generation for SEUs in the configuration memory of SRAM-based FPGA …

Communication-centric design for fmc based i/o system

M Bouain, V Viswanathan, RB Atitallah… - … -Centric Systems-on …, 2014 - ieeexplore.ieee.org
This paper presents a communication-centric reconfigurable design for FPGA Mezzanine
Card (FMC) based I/O system dedicated to several industrial application domains. The …

An efficient ber-based reliability method for sram-based fpga

F Sahraoui, F Ghaffari, MEA Benkhelifa… - 2013 8th IEEE Design …, 2013 - ieeexplore.ieee.org
Single Event Upset (SEU) is a major concern for SRAM-based FPGAs where a simple bit-flip
can lead to an abnormal execution. We present in this paper, a new fault tolerance method …

Error correction encoding for tightly coupled on-chip buses

K Karmarkar, S Tragoudas - IEEE Transactions on Very Large …, 2014 - ieeexplore.ieee.org
The performance of a tightly coupled on-chip bus connecting several embedded cores can
be improved using multithreshold comparators at the receiver end. Reduction in supply …