The embodiments of mechanisms for forming source/drain (S/D) regions of field effect
transistors (FETs) described enable forming an epitaxially grown silicon-containing layer …

In a first embodiment of the present invention, a Semi conductor device having a novel
Spacer Structure and its method of fabrication is described. According to the first …

US5908313A - Method of forming a transistor - Google Patents US5908313A - Method of
forming a transistor - Google Patents Method of forming a transistor Download PDF Info …

A novel transistor with a low resistance ultra shallow tip region and its method of fabrication
in a complementary metal oxide semiconductor (CMOS) process. According to the preferred …

(52) US Cl................... 257/24; 257/219; 257/E29. 012 (58) Field of Classification
Search.................... 257/24 See application file for complete search history. Circuits for …

US7504704B2 - Shallow trench isolation process - Google Patents US7504704B2 -
Shallow trench isolation process - Google Patents Shallow trench isolation process …

4,997,776 5,013,681 5,034,348 5,089,872 5,091,767 5,108,946 5,155,571 5,166,084
5,177.583 5, 198,689 5,202,284 5,207,864 5,208, 182 5,212,110 5,212,112 5,217.923 …

Methods and systems for permitting thickness control of the selective epitaxial growth (SEG)
layer in a semiconductor manufacturing process, for example raised source/drain …

Methods for fabricating facetless semiconductor structures using commercially available
chemical vapor deposition systems are disclosed herein. A key aspect of the invention …

US7420201B2 - Strained-semiconductor-on-insulator device structures with elevated source/drain
regions - Google Patents US7420201B2 - Strained-semiconductor-on-insulator device …