(57) ABSTRACT A method for forming a semiconductor device (100) includes a
semiconductor substrate (102) having a first region (104), forming a gate dielectric (108) …

We report the process module development results and device characteristics of dual metal
gate CMOS with TaSiN and Ru gate electrodes on HfO/sub 2/gate dielectric. The wet etch of …

We have newly developed poly-Si/a-Si/HfSiON (EOT= 1.6 nm) transistor that features high
I/sub on/-I/sub standby/ratio and reliability for 65nm-node LSTP (Low Standby Power) …

Metal–oxide-semiconductor (MOS) devices with various concentrations of La incorporation
in Hf based dielectrics were characterized to evaluate the effect of La on device performance …

For next generation MOSFETs, the constant field scaling rule dictates a reduction in the gate
oxide thickness among other parameters. Consequently, gate leakage current becomes a …

We present a low cost, single metal gate/high-k gate stack integration, which provides a very
high performing NMOS coupled with a counter-doped PMOS for a 45nm low power (LP) …

Ultra low power CMOS 6T-SRAM chips with HfO/sub 2/-Al/sub 2/O/sub 3/laminate gate
dielectric were successfully demonstrated (bit-cell size= 2.14/spl mu/m/sup 2/). Equivalent …

In this paper, we first propose an improved CVD-WSix metal gate suitable for use with
nMOSFETs. Work function of CVD-WSi3. 9 gate estimated from CV measurements was 4.3 …

Abstract According to the 2005 International Technology Roadmaps for Semiconductors
(ITRS), one of the most important challenges in the semiconductor industry is the …

In this paper field effect transistors (FETs) with new materials and new structures are
discussed. A thermal robust HfN/HfO 2 gate stack, which can alleviate the confliction …