A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the
voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in …

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS
transistors are used at the input of the first and second stages of the comparator. At the …

The ultra-low power circuits are widely applied in energy-effective systems. This paper
proposes a multi-valued adiabatic logic (MVAL) technique for energy-efficient using multiple …

An analytical method is presented to characterize stepwise adiabatic circuits (SACs). In this
method, the SACs are modeled as a discrete time system. Unlike previous methods, the …

In this paper, an analytic model of the energy consumption of the Stepwise Adiabatic Circuits
(SAC) when it is possible to discharge the load capacitor is proposed. Using this model …

A new low-power switching procedure for stepwise capacitor chargers is presented. In this
procedure, a novel displacement method is utilized to improve the speed by a factor of two …

An efficient layout technique is proposed to eliminate the effect of the bottom-plate
capacitors in a C-2C Digital to Analog Converter (DAC). Using this technique, the bottom …

There are cases in energy supply applications with low-power batteries, where the power
required by the load is larger than the supply maximum deliverable power. Using a capacitor …

A highly energy-efficiency switching procedure for the capacitor-splitting digital-to-analog
converter (DAC) is presented for successive approximation register (SAR) analogue-to …

Comparators are fundamental blocks in the architectures of analog to digital converters. Due
to the requirement of low power and high speed converters, the dynamic comparators are …