ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches
Improving result accuracy in approximate computing (AC)-based real-time applications
without violating deadlines has recently become an active research domain. Execution time …
without violating deadlines has recently become an active research domain. Execution time …
Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets
High density and low static power exhibited by nonvolatile technologies (NVM) have made
them popular candidates in the memory hierarchy, including caches. Writes within a cache …
them popular candidates in the memory hierarchy, including caches. Writes within a cache …
Efficient cache resizing policy for DRAM-based LLCs in ChipMultiprocessors
Abstract In today's ChipMultiprocessors (CMPs), multiple cores share the common Last
Level Cache (LLC), divided into multiple banks. As the data requirement is increasing the …
Level Cache (LLC), divided into multiple banks. As the data requirement is increasing the …
A Survey on Way-Based Cache Partitioning
P Das, NM Barbhuiya, BR Roy - 2023 IEEE Silchar Subsection …, 2023 - ieeexplore.ieee.org
The degree of parallelism in the systems is expected to increase, which will result in an
increase in the number of cores in chip multicore processors (CMP). As a result, in order to …
increase in the number of cores in chip multicore processors (CMP). As a result, in order to …
Lifetime enhancement of non-volatile caches by exploiting dynamic associativity management techniques
By showcasing the attractive features like high density and low static power, the emerging
Non-Volatile Memories (NVMs) have recently being accepted act as a prominent choice in …
Non-Volatile Memories (NVMs) have recently being accepted act as a prominent choice in …
A reuse-degree based locality classifier for locality-aware data replication
Q Wu, Z Ji - IEEE Access, 2019 - ieeexplore.ieee.org
The last level cache (LLC) in shared configuration is widely used in the tiled chip
multiprocessors (CMPs), which reduces the off-chip miss rate but incurs the long on-chip …
multiprocessors (CMPs), which reduces the off-chip miss rate but incurs the long on-chip …
An Improved Scheme of Victim Replication in Tiled Chip Multiprocessors
Q Wu, Z Ji - 2019 IEEE 3rd International Conference on Circuits …, 2019 - ieeexplore.ieee.org
The last level cache (LLC) in the shared configuration increases the effective cache capacity
by not allowing replication but causes a long on-chip access latency when the data is on a …
by not allowing replication but causes a long on-chip access latency when the data is on a …