Memory-aware task scheduling with communication overhead minimization for streaming applications on bus-based multiprocessor system-on-chips
Inter-core communication introduces overheads in task schedules on Multiprocessor System-
on-Chips (MPSoCs). Inter-core communication overhead not only negatively impacts the …
on-Chips (MPSoCs). Inter-core communication overhead not only negatively impacts the …
Optimally removing intercore communication overhead for streaming applications on MPSoCs
This paper aims to totally remove intercore communication overhead with joint computation
and communication task scheduling for streaming applications on Multiprocessor System-on …
and communication task scheduling for streaming applications on Multiprocessor System-on …
Optimal task scheduling by removing inter-core communication overhead for streaming applications on MPSoC
In this paper, we jointly optimize computation and communication task scheduling for
streaming applications on MPSoC. The objective is to minimize schedule length by totally …
streaming applications on MPSoC. The objective is to minimize schedule length by totally …
Quasi-static scheduling for fine-grained embedded multiprocessing
J Boutellier - 2009 - oulurepo.oulu.fi
Designing energy-efficient multiprocessing hardware for applications such as video
decoding or MIMO-OFDM baseband processing is challenging because these applications …
decoding or MIMO-OFDM baseband processing is challenging because these applications …
Memory-aware optimal scheduling with communication overhead minimization for streaming applications on chip multiprocessors
In this paper, we focus on solving the problem of removing inter-core communication
overhead for streaming applications on chip multiprocessors. The objective is to totally …
overhead for streaming applications on chip multiprocessors. The objective is to totally …
Game theoretic approach for run‐time task scheduling on an multi‐processor system on chip
K Ganeshpure, S Kundu - IET Circuits, Devices & Systems, 2013 - Wiley Online Library
Multi‐processor system on chip (MPSoC) consists of multiple cores communicating via an
on‐chip communication backplane. An application to be executed on an MPSoC is …
on‐chip communication backplane. An application to be executed on an MPSoC is …
Run-time scheduled hardware acceleration of MPEG-4 video decoding
J Boutellier, P Jaaskelainen… - … Symposium on System-on …, 2007 - ieeexplore.ieee.org
In this paper we present a hardware-accelerated system-on-chip implementation of an
MPEG-4 simple profile video decoder with a novel hardware accelerator interfacing …
MPEG-4 simple profile video decoder with a novel hardware accelerator interfacing …
Energy-efficient stream task scheduling scheme for embedded multimedia applications on multi-issued stream architectures
With the increasing requirement of computation and data amount in embedded multimedia
applications, stream architectures are exploited to accelerate the multimedia processing …
applications, stream architectures are exploited to accelerate the multimedia processing …
Overhead-aware real-time scheduling for streaming applications on multiprocessor systems-on-chip
Y Wang - 2011 - theses.lib.polyu.edu.hk
With increasing demand for high-performance multimedia in battery-driven mobile devices,
multicore architecture such as MPSoC (Multiprocessor System-on-Chip) is becoming widely …
multicore architecture such as MPSoC (Multiprocessor System-on-Chip) is becoming widely …
[图书][B] On co-optimization of constrained satisfiability problems for hardware software applications
K Ganeshpure - 2011 - search.proquest.com
Manufacturing technology has permitted an exponential growth in transistor count and
density. However, making efficient use of the available transistors in the design has become …
density. However, making efficient use of the available transistors in the design has become …