Temporal logic model checking involves checking the state-space of a model of a system to
determine whether errors can occur in the system. Often this involves checking …

Formal methods for the specification and verification of hardware and software systems are
becoming more and more important as systems increase in size and complexity. The aim of …

In this paper we study the use of Sequence Diagrams and Statecharts of the Unified
Modeling Language (UML) for the validation and the performance evaluation of systems. We …

We present a novel algorithm for generating state spaces of asynchronous systems using
Multi-valued Decision Diagrams. In contrast to related work, we encode the next-state …

This work proposes a way to model the structure and behaviour of agents in terms of
executable coloured Petri net protocols. Structure and behaviour are not all aspects of agent …

Many techniques for the verification of reactive systems rely on the analysis of their
reachable state spaces. In this paper, a new algorithm for the symbolic generation of the …

Symmetric net structure yields symmetric net behaviour. Thus, knowing the symmetries of a
net, redundant calculations can be skipped. We present a framework for the calculation of …

The state equation is a verification technique that has been applied—not always under this
name—to numerous systems modelled as Petri nets or communicating automata. Given a …

The PEP tool embeds sophisticated programming and verification components in a user-
friendly graphical interface. The basic idea is that the programming component allows the …

In spite of its informal semantics and of some ambiguities, UML is a widespread modelling
language used in both industry and academia. On the other hand, Petri nets are a …