A self-aware architecture for PVT compensation and power nap in near threshold processors

D Rossi, I Loi, A Pullini, C Müller, A Burg… - IEEE Design & …, 2017 - ieeexplore.ieee.org
As technology edges closer to fundamental limits, variations of process parameters,
operational voltage, and temperature (PVT variations) have to be accounted for. This paper …

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology

A Di Mauro, D Rossi, A Pullini… - … Symposium on Power …, 2017 - ieeexplore.ieee.org
Environmental temperature variations, as well as process variations, have a detrimental
effect on performance and reliability of embedded systems implemented with deep-sub …

Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI

A Di Mauro, D Rossi, A Pullini, P Flatresse, L Benini - Integration, 2020 - Elsevier
The performance and reliability of Ultra-Low-Power (ULP) computing platforms are
adversely affected by environmental temperature and process variations. Mitigating the …

Using transition fault test patterns for cost effective offline performance estimation

M Zandrahimi, P Debaud, A Castillejo… - … Conference on Design …, 2017 - ieeexplore.ieee.org
Process variation occurring during fabrication of complex VLSI devices induce uncertainties
in operation parameters (eg, supply voltage) to be applied to each device in order for it to fit …

具有关键路径检测功能的脉冲触发器电路及应用

石瑞恺, 王昊, 杨梁, 章隆兵 - 计算机辅助设计与图形学学报, 2019 - jcad.cn
由于在实际生产和工作过程中受到多种复杂因素的影响, 集成电路的关键路径会发生不确定的
变化. 这导致时序分析结果出现较大偏差, 芯片的硅前-硅后一致性难以保证. 为此 …

Industrial approaches for performance evaluation using on-chip monitors

M Zandrahimi, P Debaud, A Castillejo… - … International Design & …, 2016 - ieeexplore.ieee.org
To overcome the increasing sensitivity to variability in nanoscale integrated circuits,
operation parameters (eg, supply voltage) are adapted in a customized way exclusively to …

Industrial evaluation of transition fault testing for cost effective offline adaptive voltage scaling

M Zandrahimi, P Debaud, A Castillejo… - … Design, Automation & …, 2018 - ieeexplore.ieee.org
Adaptive voltage scaling (AVS) has been used widely to compensate for process, voltage,
and temperature variations as well as power optimization of integrated circuits. The current …

[PDF][PDF] Transition Fault Testing for Offline Adaptive Voltage Scaling

M Zandrahimi, P Debaud, A Castillejo, Z Al-Ars - ITC, 2017 - ce-publications.et.tudelft.nl
In this paper, we propose using transition fault test patterns to perform adaptive voltage
scaling (AVS) as a low-cost alternative to process monitoring boxes (PMBs) while improving …

Delay sensitivity polynomials based design-dependent performance monitors for wide operating ranges

R Shi, L Yang, H Wang - 2020 Design, Automation & Test in …, 2020 - ieeexplore.ieee.org
The downsizing of CMOS technology makes circuit performance more sensitive to on-chip
parameter variations. Previous proposed design-dependent ring oscillator (DDRO) method …

Pulse Flip-Flop Based Critical Path Monitor Circuit and Application

R Shi, H Wang, L Yang, L Zhang - Journal of Computer-Aided Design & …, 2019 - jcad.cn
With the influence of various complex factors in actual manufacturing and working process,
post-silicon critical paths of integrated circuit would have uncertain change. It makes large …