Nanowire array-based MOSFET for future CMOS technology to attain the ultimate scaling limit
Silicon nanowire (SiNW) structures are the essential foundations of the next generation
highly efficient and lowcost electronic devices because of their specific chemical, optical …
highly efficient and lowcost electronic devices because of their specific chemical, optical …
Investigation of CNTFET based energy efficient fast SRAM cells for edge AI devices
A novel reduced power with enhanced speed (RPES) technique for Static Random Access
Memory (SRAM) topologies using Carbon Nano Tube Field Effect Transistors (CNTFETs) …
Memory (SRAM) topologies using Carbon Nano Tube Field Effect Transistors (CNTFETs) …
Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications
Static random access memory (SRAM) cell design has undergone extensive development to
achieve good performance and low power consumption. This paper introduces an SRAM …
achieve good performance and low power consumption. This paper introduces an SRAM …
A novel approach to design SRAM cells for low leakage and improved stability
T Tripathi, DS Chauhan, SK Singh - Journal of Low Power Electronics and …, 2018 - mdpi.com
The semiconductor electronic industry is advancing at a very fast pace. The size of portable
and handheld devices are shrinking day by day and the demand for longer battery backup is …
and handheld devices are shrinking day by day and the demand for longer battery backup is …
A FinFET Based Low-Power Write Enhanced SRAM Cell With Improved Stability
This work introduces a FinFet based low-power 11T SRAM cell with write enhanced feature,
which is considered to meet modern technology requirements due to its distinctive features …
which is considered to meet modern technology requirements due to its distinctive features …
[HTML][HTML] Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS
T Ghafouri, N Manavizadeh - Alexandria Engineering Journal, 2020 - Elsevier
Abstract Designing a Static Random-Access Memory (SRAM) cell configuration that copes
with conventional complementary metal-oxide-semiconductor (CMOS) constraints on the …
with conventional complementary metal-oxide-semiconductor (CMOS) constraints on the …
Low power 8t sram with high stability and bit interleaving capability
R Lorenzo, DL Pradeep… - 2022 2nd International …, 2022 - ieeexplore.ieee.org
A new 8T Static Random-Access Memory (SRAM) presented in this paper. This paper
addresses the issue related to power, delay and bit interleaving (column selection). The …
addresses the issue related to power, delay and bit interleaving (column selection). The …
Influence of oxide thickness variation on analog and RF performances of SOI FinFET
D Tripathy, DP Acharya, PK Rout… - … Series: Electronics and …, 2022 - casopisi.junis.ni.ac.rs
This paper focuses on the impact of variation in the thickness of the oxide (SiO 2) layer on
the performance parameters of a FinFET analysed by varying the oxide layer thickness in …
the performance parameters of a FinFET analysed by varying the oxide layer thickness in …
A novel indirect read technique based SRAM with ability to charge recycle and differential read for low power consumption, high stability and performance
Read noise insertion problem of conventional read method of 6T-SRAM cell has forced to
think about indirect read. Indirect read though eliminates read noise insertion but also take …
think about indirect read. Indirect read though eliminates read noise insertion but also take …
Design and performance improvement of low power SRAM using deep submicron technology
UR Shirode, RD Kanphade - Analog Integrated Circuits and Signal …, 2023 - Springer
Static random-access memory (SRAM) is a form of random-access memory (RAM) that
stores each bit using latching circuitry (flip–flop). Embedded SRAMs take up the majority of …
stores each bit using latching circuitry (flip–flop). Embedded SRAMs take up the majority of …