In this paper, a high speed yet energy-efficient approximate divider for error resilient
applications is proposed. For the division operation, the divisor is rounded to a value with a …

Although division and square root are not frequent operations, most processors implement
them in hardware to not compromise the overall performance. Two classes of algorithms …

In this work, we present a radix-10 division unit that is based on the digit-recurrence
algorithm. The previous decimal division designs do not include recent developments in the …

This brief presents a dedicated unit for the combined operation of floating-point (FP) division
followed by addition/subtraction-the divide-add fused (DAF). The goal of this unit is to …

The unfolded and pipelined CORDIC is a high-performance hardware element that
produces a wide variety of one and two argument functions with high throughput. The …

This paper describes the hardware implementation methodologies of fixed point binary
division algorithms. The implementations have been extended for the execution of the …

The digit-recurrence division algorithm is used in several high-performance processors
because it provides good tradeoffs in terms of latency, area and power dissipation. In this …

This paper presents the detailed design of the ARM VFP11 divide and square root
synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix …

In this paper we present the algorithm and architecture a radix-10 floating-point divider
based on an SRT non-restoring digit-by-digit algorithm. The algorithm uses conventional …

Binary division operation has immense importance in the field of engineering science.
Inherently, division operation is a sequential operation, making it more expensive in terms of …