Modeling of cache access behavior based on Zipf's law
I Kotera, R Egawa, H Takizawa… - Proceedings of the 9th …, 2008 - dl.acm.org
Recently, chip multiprocessors (CMPs) that can simultaneously execute multiple workloads
using multiple cores have become a key to achieve high-performance processing. To …
using multiple cores have become a key to achieve high-performance processing. To …
Dynamic cache sharing based on power state
RD Wells, MJ Muchnick, CS Ballapuram - US Patent 9,311,245, 2016 - Google Patents
In one embodiment, the present invention includes a cache, compute engines connected to
the cache, and a way mask disposed between the cache and the compute engines. This …
the cache, and a way mask disposed between the cache and the compute engines. This …
A new edge-based text verification approach for video
In this paper, we propose a new edge-based text verification approach for video. Based on
the investigation of the relation between candidate blocks and their neighbor areas, the …
the investigation of the relation between candidate blocks and their neighbor areas, the …
Process variation aware DRAM-Cache resizing
As the demand for larger-sized Last Level Cache (LLC) grows due to modern data-intensive
applications, employing low-density SRAM technology to create the LLC for the multicore …
applications, employing low-density SRAM technology to create the LLC for the multicore …
The impact of the transparency policy on university students' trust and intention of continued use
RR Moreno, CM Molina - 2014 47th Hawaii International …, 2014 - ieeexplore.ieee.org
The loss of trust suffered by public institutions means that they are trying to identify the
existing formulae so that this can be restored, and this includes transparency. In universities …
existing formulae so that this can be restored, and this includes transparency. In universities …
Achieving fair or differentiated cache sharing in power-constrained chip multiprocessors
Limiting the peak power consumption of chip multiprocessors (CMPs) has recently received
a lot of attention. In order to enable chip-level power capping, the peak power consumption …
a lot of attention. In order to enable chip-level power capping, the peak power consumption …
Cache latency control for application fairness or differentiation in power-constrained chip multiprocessors
Limiting the peak power consumption of chip multiprocessors (CMPs) has recently received
a lot of attention. In order to enable chip-level power capping, the peak power consumption …
a lot of attention. In order to enable chip-level power capping, the peak power consumption …
Last level cache size heterogeneity in embedded systems
In typical multicore processors, last level caches are formed by distributed clusters of
memory banks of the same size, namely homogeneous ones. By shutting down part of these …
memory banks of the same size, namely homogeneous ones. By shutting down part of these …
Impact of on-chip network parameters on NUCA cache performances
Non-uniform cache architectures (NUCAs) are a novel design paradigm for large last-level
on-chip caches, which have been introduced to deliver low access latencies in wire-delay …
on-chip caches, which have been introduced to deliver low access latencies in wire-delay …
Enabling efficient dynamic resizing of large DRAM caches via a hardware consistent hashing mechanism
Die-stacked DRAM has been proposed for use as a large, high-bandwidth, last-level cache
with hundreds or thousands of megabytes of capacity. Not all workloads (or phases) can …
with hundreds or thousands of megabytes of capacity. Not all workloads (or phases) can …