Integrated circuits protected by substrates with cavities, and methods of manufacture

H Shen, CG Woychik, AR Sitaram - US Patent 10,446,456, 2019 - Google Patents
Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an
interposer, and are protected by a protective substrate (410) attached to a wiring substrate …

Vias in porous substrates

I Mohammed, B Haba, CE Uzoh, P Savalia - US Patent 9,455,181, 2016 - Google Patents
A microelectronic unit can include a substrate having front and rear surfaces and active
semiconductor devices therein, the substrate having a plurality of openings arranged in a …

Multi-chip module with stacked face-down connected dies

B Haba, I Mohammed, P Savalia - US Patent 8,841,765, 2014 - Google Patents
(57) ABSTRACT A microelectronic assembly can include a Substrate having first and
second Surfaces, at least two logic chips overlying the first surface, and a memory chip …

Tunable composite interposer

CG Woychik, CE Uzoh, H Sato - US Patent 8,963,335, 2015 - Google Patents
The present invention relates to packaging of microelec tronic devices and interposer
structures, especially conduc tive via structures and methods of forming Such via structures …

Stub minimization using duplicate sets of signal terminals

RDW Crisp, W Zohni, B Haba, F Lambrecht - US Patent 8,670,261, 2014 - Google Patents
(57) ABSTRACT A microelectronic structure has active elements defining a storage array,
and address inputs for receipt of address infor mation specifying locations within the storage …

Staged via formation from both sides of chip

V Oganesian, B Haba, I Mohammed, C Mitchell… - US Patent …, 2014 - Google Patents
2010-11-08 Assigned to TESSERA RESEARCH LLC reassignment TESSERA RESEARCH
LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS) …

Structure and method for integrated circuits packaging with increased density

CG Woychik, AR Sitaram, A Cao, BS Lee - US Patent 10,381,326, 2019 - Google Patents
(57) ABSTRACT A method of forming a semiconductor package comprises forming one or
more first vias in a first side of a substrate and attaching a first side of a first microelectronic …

Methods of forming semiconductor elements using micro-abrasive particle stream

V Oganesian, B Haba, C Mitchell, I Mohammed… - US Patent …, 2017 - Google Patents
A method of fabricating a microelectronic unit includes providing a semiconductor element
having a front Surface and a rear Surface remote from the front Surface, forming at least one …

Wire bond wires for interference shielding

A Awujoola, Z Sun, W Zohni, AS Prabhu… - US Patent …, 2017 - Google Patents
Apparatuses relating generally to a microelectronic package having protection from
interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a …

Bond via array for thermal conductivity

R Katkar, G Gao, CG Woychik, W Zohni - US Patent 9,735,084, 2017 - Google Patents
In a microelectronic device, a substrate has first upper and lower surfaces. An integrated
circuit die has second upper and lower surfaces. Interconnects couple the first upper surface …