Switching performance assessment of gate-all-around InAs–Si vertical TFET with triple metal gate, a simulation study

D Madadi, S Mohammadi - Discover Nano, 2023 - Springer
This study presents a gate-all-around InAs–Si vertical tunnel field-effect transistor with a
triple metal gate (VTG-TFET). We obtained improved switching characteristics for the …

Undoped vertical dual-bilayer TFET with a super-steep sub-threshold swing: proposal and performance comparative analysis

A Anam, SI Amin, D Prasad, N Kumar… - Semiconductor Science …, 2023 - iopscience.iop.org
In this paper, the undoped vertical dual-bilayer tunnel field effect transistor (UV-DBL-TFET)
at a low operating voltage (0.5 V) is introduced, and its DC and RF performance parameters …

Enhancement and modeling of drain current in negative capacitance double gate TFET

RK James, J Jacob, A Pradeep - Silicon, 2021 - Springer
The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect
Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region …

Design, simulation and analog/RF performance evaluation of a hetero-stacked source dual metal T-shaped gate tunnel-FET in thermally variable environments

M Kumar, G Bhaskar, A Chotalia, C Rani… - Microsystem …, 2024 - Springer
In this work, a new Hetero-Stacked Source Dual Metal T-shaped Gate Silicon-on-Insulator
(SOI) TFET (HS-DMTG-TFET) is proposed, exhibiting significantly improved DC …

Study of a Gate-Engineered Vertical TFET with GaSb/GaAs0.5Sb0.5 Heterojunction

H Xie, Y Chen, H Liu, D Guo - Materials, 2021 - mdpi.com
It is well known that the vertical tunnel field effect transistor (TFET) is easier to fabricate than
the conventional lateral TFETs in technology. Meanwhile, a lightly doped pocket under the …

Performance improvement of SOI Tunnel-FET using pure boron and Ge pocket layer

K Baruah, SMB Baruah, S Baishya - Microelectronics Journal, 2024 - Elsevier
This article highlights the results of a source pocket-engineered heterojunction pure-boron
SOI Tunnel-FET (SP-PB-TFET) for low-power applications. To achieve improved …

III-V material-based junction-free L-shaped gate normal line tunneling FET for improved performance

A Anam, SI Amin, D Prasad - Semiconductor Science and …, 2024 - iopscience.iop.org
In this paper, we introduce a novel III–V compound material-based junction-free (JF) L-
shaped gate normal line tunneling field-effect transistor (III–V JF L GNLTFET) for improved …

OFF-State Leakage Suppression in Vertical Electron–Hole Bilayer TFET Using Dual-Metal Left-Gate and N+-Pocket

H Liu, W Zhang, Z Wang, Y Li, H Zhang - Materials, 2022 - mdpi.com
In this paper, an In0. 53Ga0. 47As electron–hole bilayer tunnel field-effect transistor
(EHBTFET) with a dual-metal left-gate and an N+-pocket (DGNP-EHBTFET) is proposed and …

A symmetric heterogate dopingless electron-hole bilayer TFET with ferroelectric and barrier layers

H Liu, X Zhou, P Li, P Wang, Y Li, L Pan… - Physica Scripta, 2024 - iopscience.iop.org
In this paper, a symmetric heterogate dopingless electron–hole bilayer tunnel field-effect
transistor with a ferroelectric layer and a dielectric barrier layer (FBHD-EHBTFET) is …

Design and performance enhancement of vertical nanowire TFET using triple metal gate technique

A Bhardwaj, P Kumar, B Raj… - … Conference on Disruptive …, 2021 - ieeexplore.ieee.org
In this paper, Triple Metal Gate technique based Vertical Nanowire TFET (TMG-VNWTFET)
is proposed and its performance characteristics are analyzed. The proposed device is …