Design space exploration and implementation of a high performance and low area coarse grained reconfigurable processor

D Suh, K Kwon, S Kim, S Ryu… - … conference on field …, 2012 - ieeexplore.ieee.org
Coarse Grained Reconfigurable Architectures (CGRAs) have played a key role in the area of
domain specific processors due to their programmability and runtime reconfigurability. The …

[图书][B] Scheduling techniques for high-throughput loop accelerators

F Hannig - 2009 - cs12.tf.fau.de
The desire for more mobility and the enthusiasm for ubiquitous electronic gadgets on the
one hand side and the steady progress in semiconductor industry on the other hand are the …

Block-matching correlation motion estimation for frame-rate up-conversion

VB Kovačević, Z Pantić, A Berić… - Journal of Signal …, 2016 - Springer
This paper proposes a novel motion estimation algorithm that combines recursive block-
matching and customized phase plane correlation. In comparison with alternative …

New access modes of parallel memory subsystem for sub-pixel motion estimation

R Jakovljević, A Berić, E Van Dalen… - Journal of Real-Time …, 2018 - Springer
Accessing pixels in memory is a well-known bottleneck of SIMD (single instruction multiple
data) processors in video/imaging. To tackle it, we propose new block and row access …

A reconfigurable high performance asip engine for image signal processing

H Liao, M Asri, T Isshiki, D Li… - 2012 IEEE 26th …, 2012 - ieeexplore.ieee.org
Emerging digital television applications and the conventional MPSoC architectures
encounter drastically increasing performance and flexibility requirement. To display high …

A high level design of reconfigurable and high-performance ASIP engine for image signal processing

HC Liao, M Asri, T Isshiki, D Li… - IEICE Transactions on …, 2012 - search.ieice.org
Emerging image and video applications and conventional MPSoC architectures encounter
drastically increasing performance and flexibility requirements. In order to display high …

Design and tool flow of multimedia MPSoC platforms

B De Sutter, D Verkest, E Brockmeyer… - Journal of Signal …, 2009 - Springer
This paper surveys components that are useful to build programmable, predictable,
composable, and scalable multiprocessor-system-on-a-chip (MPSoC) multimedia platforms …

The eISP low-power and tiny silicon footprint programmable video architecture

M Thevennin, M Paindavoine, L Letellier… - Journal of Real-Time …, 2011 - Springer
CMOS sensors are now more and more frequently integrated into popular consumer
products. Images from these sensors thus need to be digitally processed for display …

Etude et conception d'un réseau sur puce dynamiquement adaptable pour la vision embarquée

N Ngan - 2011 - pastel.hal.science
Un équipement portable moderne intègre plusieurs capteurs d'image qui peuvent être de
différents types. On peut citer en guise d'exemple un capteur couleur, un capteur infrarouge …

A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine

HC Liao, M Asri, T Isshiki, D Li… - IEICE Transactions on …, 2013 - search.ieice.org
Image processing engine is crucial for generating high quality images in video system. As
Application Specific Integrated Circuit (ASIC) is dedicated for specific standards, Application …