Homomorphic encryption (HE) enables the secure offloading of computations to the cloud by
providing computation on encrypted data (ciphertexts). HE is based on noisy encryption …

The memory system is a major performance determinant for server processors. Ever-
growing core counts and datasets demand higher bandwidth and capacity as well as lower …

In this article, a configurable and highly flexible four-level pulse amplitude modulation
(PAM4) serializer/deserializer (SerDes) simulation system based on a field-programmable …

This brief presents a 2.5–32 Gb/s Gen 5-PCIe receiver with a multi-rate clock and data
recovery (CDR) engine and a hybrid decision feedback equalizer (DFE). The receiver for the …

A 10–26 Gb/s energy-efficient receiver incorporating a dual-feedback nested loop clock and
data recovery circuit (DF-CDR) is proposed. Combining a direct modulation path on voltage …

Demand for higher aggregate data rates in digital computing and storage services requires
higher per-lane throughput, better reliability, and improved power-and area-efficiency …

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for
multiple industrial protocols and compatible with different protocol versions. Targeting a …

This paper presents a 32Gbps wireline transceiver that not only supports the JESD204C
standard but also maintains back-compatibility with JESD204B with minimal additional …

The slowdown of Moore's Law has decreased the rate that transistor density has been
increasing in silicon chips. These circumstances increasingly force computer architects to …

The rapid increase in integrated circuit complexity has led to an increase in the amount of
data transferred between chips. However, increasing the amount of input/output pins to …