Large cloud service providers have invested in increasingly larger datacenters to house the
computing infrastructure required to support their services. Accordingly, researchers and …

The Wisconsin Multifacet Project has created a simulation toolset to characterize and
evaluate the performance of multiprocessor hardware systems commonly used as database …

This paper studies the impact of L2 cache sharing on threads that simultaneously share the
cache, on a chip multi-processor (CMP) architecture. Cache sharing impacts threads …

Modern processors use two or more levels ofcache memories to bridge the rising disparity
betweenprocessor and memory speeds. Compression canimprove cache performance by …

Debuggers have been proven indispensable in improving software reliability. Unfortunately,
on most real-life software, debuggers fail to deliver their most essential feature---a faithful …

This paper presents CMP Cooperative Caching, a unified framework to manage a CMP's
aggregate on-chip cache resources. Cooperative caching combines the strengths of private …

This paper proposes a hardware transactional memory (HTM) system called LogTM
Signature Edition (LogTM-SE). LogTM-SE uses signatures to summarize a transactions read …

In response to increasing (relative) wire delay, architects have proposed various
technologies to manage the impact of slow wires on large uniprocessor L2 caches. Block …

This paper presents a systematic approach to identify and quantify the types of structures
featured by packet traces in communication networks. Our approach leverages an …

Smartphones have recently overtaken PCs as the primary consumer computing device in
terms of annual unit shipments. Given this rapid market growth, it is important that mobile …