Multiple networks have been used in several processor implementations to scale bandwidth
and ensure protocol-level deadlock freedom for different message classes. In this paper, we …

NoCs are an integral part of modern multicore processors, they must continuously support
high-throughput low-latency on-chip data communication under a stringent energy budget …

Hybrid Wireless Network-on-Chip (HWNoC) architecture has been introduced as a
promising communication infrastructure for multicore systems. HWNoC-based multicore …

On-chip networks are especially vulnerable to within-die parameter variations. Since they
connect distant parts of the chip, they need to be designed to work under the most …

Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints
in the traditional electrical interconnections. However, the occurrence of faults has become …

Abstract Wireless Networks-on-Chip (WiNoC) architecture has emerged as an alternative
communication infrastructure for the conventional wire-line NoC to achieve higher …

Sequential consistency is arguably the most intuitive memory consistency model for shared-
memory multi-threaded programming, yet it appears to be a poor fit for simple, in-order …

Wireless Network-on-Chip (WNoC) architectures have emerged as a promising
interconnection infrastructure to address the performance limitations of traditional wire …

The development of nanophotonics in the last decades indicates a good opportunity for
constructing the opto-electronic networks on chip. Hybrid opto-electronic network-on-chip …

Abstract Hybrid Wireless Network on Chip (WNoC) architecture has been proposed as a
promising solution for addressing on-chip communication problems in many multicore …