Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

S Nemati, M Haghi Kashani… - IET Circuits, Devices & …, 2023 - Wiley Online Library
The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude
of ternary full adders (TFAs) have been presented in the literature. This article conducts a …

Memristor-based balanced ternary adder

AA El-Slehdar, AH Fouad… - 2013 25th International …, 2013 - ieeexplore.ieee.org
This paper introduces a memristor based ternary adder, which is an essential building block
for any arithmetic ternary operations. The proposed ternary adder circuit tries to achieve the …

Arithmetic with binary-encoded balanced ternary numbers

B Parhami, M McKeown - 2013 Asilomar Conference on …, 2013 - ieeexplore.ieee.org
Ternary number representation and arithmetic, based on the radix-3 digit set {-1, 0,; 1}, has
been studied at various times in the history of digital computing. Some such studies …

Modeling of polarization-conversion and rotation-based ultrafast All-optical ternary logic switch using microring resonator

MP Singh, JK Rakshit, M Hossain - Brazilian Journal of Physics, 2023 - Springer
In the present work, polarization conversion and rotation (PCR) based on a ternary logic for
an optical switch has been proposed and described. The proposed design utilizes GaAs …

Balanced ternary logic gates with memristors

M Diwan, Z Li, G Schiele… - 2022 29th IEEE …, 2022 - ieeexplore.ieee.org
Classical binary computing technology utilises tran-sistor scaling for improved performance.
However, with predicted limits of transistor scaling, alternative logic systems like ternary …

Implantation of polarization rotation based ternary 3: 1 multiplexer and 1: 3 demultiplexer using optical micro ring resonator

MP Singh, JK Rakshit, M Hossain - Optics Communications, 2022 - Elsevier
All optical ternary 3: 1 multiplexer and 1: 3 demultiplexer circuits are proposed and
explained using polarization rotation switch (PRS) in micro ring resonator (MRR). Ternary …

Designing of an all-optical scheme for single input ternary logical operations

C Taraphdar, T Chattopadhyay, JN Roy - Optik, 2011 - Elsevier
In this paper, for the first time to our knowledge, we propose and describe a novel design of
single circuit capable of generating all the possible 27 logic functions for single input ternary …

Truncated ternary multipliers

B Parhami - IET Computers & Digital Techniques, 2015 - Wiley Online Library
Balanced ternary number representation and arithmetic, based on the symmetric radix‐3
digit set {− 1, 0,+ 1}, has been studied at various times in the history of computing. Among …

Fast addition using balanced ternary counters designed with CMOS semi-floating gate devices

H Gundersen, Y Berg - … on Multiple-Valued Logic (ISMVL'07), 2007 - ieeexplore.ieee.org
This paper presents ternary counters using balanced ternary notation. The balanced ternary
counters can replace binary full adders or counters in fast adder structures. The circuits use …

A balanced ternary multiplication circuit using recharged semi-floating gate devices

H Gundersen, Y Berg - 2006 NORCHIP, 2006 - ieeexplore.ieee.org
This paper presents a multiplier circuit using balanced ternary (BT) notation. The multiplier
can multiply both negative and positive numbers, which is one of the advantage able …