High-speed and energy-efficient carry look-ahead adder
P Balasubramanian, NE Mastorakis - Journal of Low Power Electronics …, 2022 - mdpi.com
The carry look-ahead adder (CLA) is well known among the family of high-speed adders.
However, a conventional CLA is not faster than other high-speed adders such as a …
However, a conventional CLA is not faster than other high-speed adders such as a …
Factorized carry lookahead adders
P Balasubramanian, DL Maskell - … International Symposium on …, 2019 - ieeexplore.ieee.org
New factorized carry lookahead adders corresponding to the regular carry lookahead adder
(RCLA) architecture viz. the factorized regular carry lookahead adder (FRCLA), and the …
(RCLA) architecture viz. the factorized regular carry lookahead adder (FRCLA), and the …
Design and Implementation of RNB multiplier Using NP Domino logic
In this paper, a Reordered Normal Basis (RNB) finite field multiplier is implemented using
NP domino logic. This multiplier uses RNB, which is the type-II Optimal Normal Basis (ONB) …
NP domino logic. This multiplier uses RNB, which is the type-II Optimal Normal Basis (ONB) …
A comparison of high-frequency 32-bit dynamic adders with conventional silicon and novel carbon nanotube transistor technologies
The performances of high-frequency two-stage pipeline 32-bit carry lookahead adders are
evaluated in this paper with the following three different implementations: silicon MOSFET …
evaluated in this paper with the following three different implementations: silicon MOSFET …
MITH-Dyn: A multi Vth dynamic logic design style using mixed mode FinFETs
R Nair, R Vemuri - 2014 27th IEEE International System-on …, 2014 - ieeexplore.ieee.org
In FinFETs, the back-gate of the transistor can be biased to control its V th, thereby reducing
leakage power at the expense of performance. This paper proposes a novel multi V th …
leakage power at the expense of performance. This paper proposes a novel multi V th …
[PDF][PDF] DESIGN AND IMPLEMENTATION OF LOW POWER NOISE TOLERANCE CIRCUIT TECHNIQUE FOR DOMINO LOGIC
RK Patjoshi - researchgate.net
The difficulty of future computing, in addition to the challenges of nanometer-era of VLSI
design require new CMOS logic techniques and styles that are at the same time high …
design require new CMOS logic techniques and styles that are at the same time high …
Design and Analysis of Improved Domino Logic with Noise Tolerance and High Performance
P Meher - 2014 - ethesis.nitrkl.ac.in
The demands of upcoming computing, as well as the challenges of nanometer-era of VLSI
design necessitate new digital logic techniques and styles that are at the same time high …
design necessitate new digital logic techniques and styles that are at the same time high …