[图书][B] Advanced signal integrity for high-speed digital designs
SH Hall, HL Heck - 2011 - books.google.com
A synergistic approach to signal integrity for high-speed digital design This book is designed
to provide contemporary readers with an understanding of the emerging high-speed signal …
to provide contemporary readers with an understanding of the emerging high-speed signal …
[图书][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization
T Beukema, M Sorna, K Selander, S Zier… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
A 4.9-6.4-Gb/s two-level SerDes ASIC I/O core employing a four-tap feed-forward equalizer
(FFE) in the transmitter and a five-tap decision-feedback equalizer (DFE) in the receiver has …
(FFE) in the transmitter and a five-tap decision-feedback equalizer (DFE) in the receiver has …
A scalable 5–15 Gbps, 14–75 mW low-power I/O transceiver in 65 nm CMOS
G Balamurugan, J Kennedy, G Banerjee… - IEEE Journal of Solid …, 2008 - ieeexplore.ieee.org
We present a scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps
operation over single-board and backplane FR4 channels with power efficiencies between …
operation over single-board and backplane FR4 channels with power efficiencies between …
A 19-Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45-nm SOI CMOS
A Agrawal, JF Bulzacchelli, TO Dickson… - IEEE journal of solid …, 2012 - ieeexplore.ieee.org
This paper presents the design of a 19-Gb/s serial link receiver with both 4-tap feed-forward
equalizer (FFE) and 5-tap decision-feedback equalizer (DFE), thereby making the …
equalizer (FFE) and 5-tap decision-feedback equalizer (DFE), thereby making the …
[图书][B] Channel-limited high-speed links: Modeling, analysis and design
V Stojanovic - 2005 - search.proquest.com
Today's high-speed interfaces are limited by the bandwidth of the communication channel,
tight power constraints and noise sources that differ from those in standard communication …
tight power constraints and noise sources that differ from those in standard communication …
A 10Gb/s CMOS adaptive equalizer for backplane applications
S Gondi, J Lee, D Takeuchi… - ISSCC. 2005 IEEE …, 2005 - ieeexplore.ieee.org
A 10Gb/s CMOS adaptive equalizer for backplane applications Page 1 328 • 2005 IEEE
International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 ©2005 IEEE. ISSCC …
International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 ©2005 IEEE. ISSCC …
A low-power, 20-Gb/s continuous-time adaptive passive equalizer
R Sun, J Park, F O'Mahony… - 2005 IEEE International …, 2005 - ieeexplore.ieee.org
This paper describes a 20-Gb/s continuous-time adaptive passive equalizer utilizing on-chip
lumped RLC components. Passive equalizers offer the advantages of higher bandwidth and …
lumped RLC components. Passive equalizers offer the advantages of higher bandwidth and …
A 2.5-to 3.5-Gb/s Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line in 0.25-$ muhbox m $ CMOS
This paper presents an adaptive finite impulse response (FIR) equalizer with continuous-
time wide-bandwidth delay line in CMOS 0.25-mum process for 2.5-Gb/s to 3.5-Gb/s data …
time wide-bandwidth delay line in CMOS 0.25-mum process for 2.5-Gb/s to 3.5-Gb/s data …
Power optimized ADC-based serial link receiver
EH Chen, R Yousry, CKK Yang - IEEE Journal of Solid-State …, 2012 - ieeexplore.ieee.org
Implementing serial I/O receivers based on analog-to-digital converters (ADCs) and digital
signal post-processing has drawn growing interest with technology scaling, but power …
signal post-processing has drawn growing interest with technology scaling, but power …