Recent advances on HEVC inter-frame coding: From optimization to implementation and beyond
High Efficiency Video Coding (HEVC) has doubled the video compression ratio with
equivalent subjective quality as compared to its predecessor H. 264/AVC. The significant …
equivalent subjective quality as compared to its predecessor H. 264/AVC. The significant …
Power-efficient sum of absolute differences hardware architecture using adder compressors for integer motion estimation design
Sum of absolute differences (SAD) calculation is one of the most time-consuming operations
of video encoders compatible with the high efficiency video coding standard. SAD hardware …
of video encoders compatible with the high efficiency video coding standard. SAD hardware …
[HTML][HTML] Algorithm and architecture design of the motion estimation for the H. 265/HEVC 4K-UHD encoder
G Pastuszak, M Trochimiuk - Journal of Real-Time Image Processing, 2016 - Springer
This paper presents the algorithm and the architecture of the high-throughput motion
estimation system for the H. 265/HEVC encoder. The design allows the processing of …
estimation system for the H. 265/HEVC encoder. The design allows the processing of …
Hardware implementation for the HEVC fractional motion estimation targeting real-time and low-energy
This paper presents an energy-aware and high-throughput hardware design for the
Fractional Motion Estimation (FME) compliant with the High Efficiency Video Coding (HEVC) …
Fractional Motion Estimation (FME) compliant with the High Efficiency Video Coding (HEVC) …
A reconfigurable hardware architecture for fractional pixel interpolation in high efficiency video coding
We present a novel reconfigurable hardware architecture for interpolation filtering in high
efficient video coding that adapts to run-time changes of the number of interpolation filter …
efficient video coding that adapts to run-time changes of the number of interpolation filter …
Challenging the best HEVC fractional pixel FPGA interpolators with reconfigurable and multifrequency approximate computing
Applicable in different fields and markets, low energy high efficiency video coding (HEVC)
codecs and their constituting elements have been heavily studied. Fractional pixel …
codecs and their constituting elements have been heavily studied. Fractional pixel …
[HTML][HTML] Architecture design of the high-throughput compensator and interpolator for the H. 265/HEVC encoder
G Pastuszak, M Trochimiuk - Journal of Real-Time Image Processing, 2016 - Springer
This paper presents the architecture of the high-throughput compensator and the
interpolator used in the motion estimation of the H. 265/HEVC encoder. The architecture can …
interpolator used in the motion estimation of the H. 265/HEVC encoder. The architecture can …
Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding
The sum of absolute difference (SAD) calculation is one of the most computing-intensive
operations in video encoders compatible with recent standards, such as high-efficiency …
operations in video encoders compatible with recent standards, such as high-efficiency …
Low-power and memory-aware approximate hardware architecture for fractional motion estimation interpolation on HEVC
Nowadays, current video coding standards like the High Efficiency Video Coding (HEVC)
implement several complex coding tools, like the Fractional Motion Estimation (FME). An …
implement several complex coding tools, like the Fractional Motion Estimation (FME). An …
A QFHD 30-frames/s HEVC decoder design
PT Chiang, YC Ting, HK Chen, SY Jou… - … on Circuits and …, 2015 - ieeexplore.ieee.org
The High Efficiency Video Coding (HEVC) standard provides superior compression with
large and variablesize coding units and advanced prediction modes, which leads to high …
large and variablesize coding units and advanced prediction modes, which leads to high …