A low power and high linearity UWB low noise amplifier (LNA) for 3.1–10.6 GHz wireless applications in 0.13 μm CMOS process

H Rastegar, S Saryazdi, A Hakimi - Microelectronics journal, 2013 - Elsevier
In this paper, a low power ultra-wideband (UWB) CMOS LNA was designed exploiting
source inductive degeneration technique operating in the frequency range of 3.1–10.6 GHz …

Battery-Free 802.15. 4 Receiver

C Pérez-Penichet, C Noda… - 2018 17th ACM/IEEE …, 2018 - ieeexplore.ieee.org
We present the architecture of an 802.15. 4 receiver that, for the first time, operates at a few
hundred microwatts, enabling new battery-free applications. To reach the required micro …

A High linearity CMOS low noise amplifier for 3.66 GHz applications using current-reused topology

H Rastegar, A Hakimi - Microelectronics Journal, 2013 - Elsevier
A narrow band CMOS low noise amplifier (LNA) achieving high third-order input intercept
point (IIP3) is proposed exploiting a non-linearity cancelation technique at RF frequency. In …

A multi-band low noise amplifier with wide-band interference rejection improvement

JJ Wang, DY Chen, SF Wang, RS Wei - AEU-International Journal of …, 2016 - Elsevier
In this paper, a differential multi-band CMOS low noise amplifier (LNA), operated in a range
of 800–1700 MHz, is proposed. In this design, the LNA is integrated wide-band interference …

Designing and modeling of ultra low voltage and ultra low power LNA using ANN and ANFIS for Bluetooth applications

G Karimi, SB Sedaghat, R Banitalebi - Neurocomputing, 2013 - Elsevier
This paper reports the design of an ultra low voltage and ultra low power RF CMOS LNA
using a two-stage common source-common gate topology with source inductive …

Harmonic analysis of CMOS low noise amplifier with employing PMOS IMD technique for biosensor applications

Jyoti, R Pandey, NS Raghava - Microsystem Technologies, 2023 - Springer
A narrowband cascode inductive degeneration CMOS low-noise amplifier (LNA) with post-
distortion (PD) linearization technique is designed by TSMC CMOS 180 nm technology for …

A 2 GHz 20 dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique

H Rastegar, JH Lim, JY Ryu - JSTS: Journal of Semiconductor …, 2016 - koreascience.kr
The linearization technique for low noise amplifier (LNA) has been implemented in standard
$0.18-{\mu} m $ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique …

Low‐power and low‐noise complementary metal oxide semiconductor distributed amplifier using the gain‐peaking technique

R Izadi Saadi, A Hakimi - International Journal of Circuit Theory …, 2017 - Wiley Online Library
This paper presents an improved topology for ultra‐low‐power complementary metal oxide
semiconductor (CMOS) distributed amplifier (DA) based on modified folded cascode gain …

A low power CMOS UWB LNA with dual-band notch filter using forward body biasing

M Babasafari, M Yargholi - IETE Journal of Research, 2020 - Taylor & Francis
In this paper, two ultra-wide band (UWB) low noise amplifiers (LNAs) with out-of-band
rejection between 2.4–10.2 GHz and forward body biasing technique for wideband …

A novel automated MOALO algorithm aided RF low‐noise amplifier design for wireless applications

S Suvitha, JM Mathana - Concurrency and Computation …, 2019 - Wiley Online Library
This paper presents a Novel automated Multi Objective Ant Lion Optimization Algorithm
(MOALO) aided Radio Frequency Low Noise Amplifier (RFLNA) design for wireless …