In-memory computing integrated structure circuit based on nonvolatile flash memory unit

P Xu, D Lan, F Wang, I Shin - Electronics, 2023 - mdpi.com
Artificial intelligence has made people's demands for computer computing efficiency
increasingly high. The traditional hardware circuit simulation method for neural morphology …

An astrocyte-flow mapping on a mesh-based communication infrastructure to defective neurons phagocytosis

AM Rahmani, R Ali Naqvi, S Ali… - Mathematics, 2021 - mdpi.com
In deploying the Internet of Things (IoT) and Internet of Medical Things (IoMT)-based
applications and infrastructures, the researchers faced many sensors and their output's …

A Low-Cost Training Method of ReRAM Inference Accelerator Chips for Binarized Neural Networks to Recover Accuracy Degradation due to Statistical Variabilities

Z Chen, T Ohsawa - IEICE Transactions on Electronics, 2022 - search.ieice.org
A new software based in-situ training (SBIST) method to achieve high accuracies is
proposed for binarized neural networks inference accelerator chips in which measured …

A Fully Analog Deep Neural Network Inference Accelerator with Pipeline Registers Based on Master-Slave Switched Capacitors

Y Mei, T Ohsawa - IEICE Transactions on Electronics, 2023 - search.ieice.org
A fully analog pipelined deep neural network (DNN) accelerator is proposed, which is
constructed by using pipeline registers based on master-slave switched capacitors. The idea …

A training method for deep neural network inference accelerators with high tolerance for their hardware imperfection

S Gao, T Ohsawa - Japanese Journal of Applied Physics, 2024 - iopscience.iop.org
We propose a novel training method named hardware-conscious software training (HCST)
for deep neural network inference accelerators to recover the accuracy degradation due to …