More is less: Domain-specific speech recognition microprocessor using one-dimensional convolutional recurrent neural network

B Liu, H Cai, Z Zhang, X Ding, Z Wang… - … on Circuits and …, 2021 - ieeexplore.ieee.org
Low-power keywords recognition has been a focus of acoustic signal processing for several
decades. This work investigates the domain-specific speech recognition microprocessor …

A 6 mW, 5,000-word real-time speech recognizer using WFST models

M Price, J Glass… - IEEE Journal of Solid-State …, 2014 - ieeexplore.ieee.org
We describe an IC that provides a local speech recognition capability for a variety of
electronic devices. We start with a generic speech decoder architecture that is …

Layer-Wise Mixed-Modes CNN Processing Architecture With Double-Stationary Dataflow and Dimension-Reshape Strategy

B Liu, X Huang, Y Zhang, G Yang, H Yan… - … on Circuits and …, 2024 - ieeexplore.ieee.org
With the development of convolutional neural networks (CNN) across various domains, the
growth in network structure complexity and computational load has increasingly become a …

A fixed-point neural network architecture for speech applications on resource constrained hardware

M Shah, S Arunachalam, J Wang, D Blaauw… - Journal of Signal …, 2018 - Springer
Speech recognition and keyword detection are becoming increasingly popular applications
for mobile systems. These applications have large memory and compute resource …

Timing Error Tolerant CNN Accelerator With Layer-Wise Approximate Multiplication

B Liu, N Xie, Q Wei, G Yang, C Xie… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Exploiting the error tolerance in computation, approximate circuits become an emerging
computing paradigm to increase the energy efficiency in digital systems, which is crucial in …

Energy-scalable speech recognition circuits

M Price - 2016 - dspace.mit.edu
As people become more comfortable with speaking to machines, the applications of speech
interfaces will diversify and include a wider range of devices, such as wearables …

Time-encoding-based ultra-low power features extraction circuit for speech recognition tasks

E Gutierrez, C Perez, F Hernandez, L Hernandez - Electronics, 2020 - mdpi.com
Current trends towards on-edge computing on smart portable devices requires ultra-low
power circuits to be able to make feature extraction and classification tasks of patterns. This …

[PDF][PDF] Memory-Efficient Modeling and Search Techniques for Hardware ASR Decoders.

M Price, AP Chandrakasan, JR Glass - Interspeech, 2016 - isca-archive.org
This paper gives an overview of acoustic modeling and search techniques for low-power
embedded ASR decoders. Our design decisions prioritize memory bandwidth, which is the …

Reduced memory viterbi decoding for hardware-accelerated speech recognition

PP Raj, PA Reddy, N Chandrachoodan - ACM Transactions on …, 2022 - dl.acm.org
Large Vocabulary Continuous Speech Recognition systems require Viterbi searching
through a large state space to find the most probable sequence of phonemes that led to a …

A 40-NM 54-MW 3×-real-time VLSI processor for 60-kWord continuous speech recognition

G He, Y Miyamoto, K Matsuda, S Izumi… - SiPS 2013 …, 2013 - ieeexplore.ieee.org
This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous
speech recognition based on a context-dependent Hidden Markov Model (HMM). We …