This paper reviews the design challenges and techniques of high-performance SRAM in the
“End of Scaling” nanoscale CMOS technologies. The impacts of technology scaling, such as …

In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive
feedback sensing keeper schemes are proposed to improve the read static noise margin …

Minimum energy operation for digital circuits typically requires scaling the power supply
below the device threshold voltage. Advanced technologies offer improved integration …

Variation in transistor characteristics is increasing as CMOS transistors are scaled to
nanometer feature sizes. This increase in transistor variability poses a serious challenge to …

A 512Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179 µm 2 cell, which
is 10% smaller than the SRAM scaling trend. The smaller cell size is realized by channel …

This paper compares area scaling capabilities of many kinds of SRAM margin-assist
solutions for VT variability issues, which are based on various efforts by not only the cell …

In this paper, approximate SRAMs are explored in the context of error-tolerant applications,
in which energy is saved at the cost of the occurrence of read/write errors (ie, signal quality …

We propose an access scheme for a synchronous dual-port (DP) SRAM that minimizes the
8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bit-line …

The variation tolerant assist circuits of an SRAM against process and temperature are
proposed. Passive resistances are introduced to the read assist circuit with replica memory …

The minimum operating voltage, V min, of nanoscale CMOS LSIs is investigated to breach
the 1-V wall that we are facing in the 65-nm device generation, and open the door to the …