A first-step half-reference ramping (FHR) readout scheme is presented in this study for high
frame rate CMOS image sensors (CISs). The proposed readout scheme enhances the …

This paper presents a power-saving readout scheme for CMOS image sensors (CISs) that
utilizes the image properties. The proposed delta-readout (A-readout) scheme reads the …

This paper presents an area-efficient and low-power 12-b successive approximation
register/single-slope analog-todigital converter (SAR/SS ADC) for CMOS image sensor …

This paper proposes a low-power column-parallel two-step single slope Analog-to-Digital
Converter (SS ADC) and voltage range tuned ramp generator for low-power CMOS Image …

This work presents a hybrid column-parallel time-to-digital-converter interpolated (TDC)
single-slope (SS) ADC with a digital delay element feedback. The proposed scheme solves …

This paper presents a low-voltage and power-efficient 10 bit successive-approximation
register (SAR) analog-to-digital converter (ADC). The input-range-adaptive (IRA) switching …

This article presents an ultra-low power counter structure for a column-parallel single-slope
analog-to-digital converter (SS-ADC) in CMOS image sensors. The proposed counter …

This paper proposes a novel 12-bit column-parallel two-step single-slope (SS) analog-to-
digital converter (ADC) for high-speed CMOS image sensors. Cooperating with the output …

A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with
pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is …

Huge advancements have been made over the years in terms of modern image-sensing
hardware and visual computing algorithms (eg, computer vision, image processing, and …