Overview and outlook of three-dimensional integrated circuit packaging, three-dimensional Si integration, and three-dimensional integrated circuit integration
JH Lau - Journal of Electronic Packaging, 2014 - asmedigitalcollection.asme.org
3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC
integration. They are different and in general the through-silicon via (TSV) separates 3D IC …
integration. They are different and in general the through-silicon via (TSV) separates 3D IC …
Evolution, challenge, and outlook of TSV, 3D IC integration and 3D silicon integration
JH Lau - … symposium on advanced packaging materials (APM), 2011 - ieeexplore.ieee.org
3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They
are different and in general the TSV (through-silicon via) separates 3D IC packaging from …
are different and in general the TSV (through-silicon via) separates 3D IC packaging from …
3D integration review
D integration delivers value by increasing the volumetric transistor density with the potential
benefit of shorter electrical path lengths through use of the shorter third dimension. Several …
benefit of shorter electrical path lengths through use of the shorter third dimension. Several …
Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric
T Frank, S Moreau, C Chappaz, P Leduc… - Microelectronics …, 2013 - Elsevier
In this paper, reliability of Through Silicon via (TSV) interconnects is analyzed for two
technologies. First part presents an exhaustive analysis of Cu TSV-last approach of 2μm …
technologies. First part presents an exhaustive analysis of Cu TSV-last approach of 2μm …
Study on Cu protrusion of through-silicon via
The through-silicon via (TSV) approach is essential for 3-D integrated circuit (3-DIC)
packaging technology. TSV fabrication process, however, is still facing several challenges …
packaging technology. TSV fabrication process, however, is still facing several challenges …
A detailed failure analysis examination of the effect of thermal cycling on Cu TSV reliability
C Okoro, JW Lau, F Golshany… - … on Electron Devices, 2013 - ieeexplore.ieee.org
In this paper, the reliability of through-silicon via (TSV) daisy chains under thermal cycling
conditions was examined. The electrical resistance of TSV daisy chains was found to …
conditions was examined. The electrical resistance of TSV daisy chains was found to …
3D Integration
JH Lau, JH Lau - Fan-Out Wafer-Level Packaging, 2018 - Springer
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Find a journal Publish with us Track your research Search Cart Book cover Fan-Out …
Find a journal Publish with us Track your research Search Cart Book cover Fan-Out …
Analytical fault tolerance assessment and metrics for TSV-based 3D network-on-chip
Reliability is one of the most challenging problems in the context of three-dimensional
network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the …
network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the …
An end-to-end convolutional neural network for automated failure localisation and characterisation of 3D interconnects
P Paulachan, J Siegert, I Wiesler, R Brunner - Scientific Reports, 2023 - nature.com
The advancement in the field of 3D integration circuit technology leads to new challenges for
quality assessment of interconnects such as through silicon vias (TSVs) in terms of …
quality assessment of interconnects such as through silicon vias (TSVs) in terms of …
Architecture of ring-based redundant TSV for clustered faults
WH Lo, K Chi, TT Hwang - IEEE Transactions on Very Large …, 2016 - ieeexplore.ieee.org
Three-dimensional integrated circuits (3-D-ICs) that employ the through-silicon vias (TSVs)
vertically stacking multiple dies provide many benefits, such as high density, high …
vertically stacking multiple dies provide many benefits, such as high density, high …