A survey of timing verification techniques for multi-core real-time systems

C Maiza, H Rihani, JM Rivas, J Goossens… - ACM Computing …, 2019 - dl.acm.org
This survey provides an overview of the scientific literature on timing verification techniques
for multi-core real-time systems. It reviews the key results in the field from its origins around …

Contention in multicore hardware shared resources: Understanding of the state of the art

G Fernandez, J Abella, E Quiñones… - … Workshop on Worst …, 2014 - hal.science
The real-time systems community has over the years devoted considerable attention to the
impact on execution timing that arises from contention on access to hardware shared …

A coordinated approach for practical OS-level cache management in multi-core real-time systems

H Kim, A Kandhalu, R Rajkumar - 2013 25th Euromicro …, 2013 - ieeexplore.ieee.org
Many modern multi-core processors sport a large shared cache with the primary goal of
enhancing the statistic performance of computing workloads. However, due to resulting …

SecureCore: A multicore-based intrusion detection architecture for real-time embedded systems

MK Yoon, S Mohan, J Choi, JE Kim… - 2013 IEEE 19th Real …, 2013 - ieeexplore.ieee.org
Security violations are becoming more common in real-time systems-an area that was
considered to be invulnerable in the past-as evidenced by the recent W32. Stuxnet and …

A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems

M Hassan, H Patel, R Pellizzoni - 21st IEEE Real-Time and …, 2015 - ieeexplore.ieee.org
Mixed-time critical systems are real-time systems that accommodate both hard real-time
(HRT) and soft realtime (SRT) tasks. HRT tasks mandate a gurantee on the worstcase …

Fault-tolerant and real-time scheduling for mixed-criticality systems

RM Pathan - Real-Time Systems, 2014 - Springer
The design and analysis of real-time scheduling algorithms for safety-critical systems is a
challenging problem due to the temporal dependencies among different design constraints …

Criticality-and requirement-aware bus arbitration for multi-core mixed criticality systems

M Hassan, H Patel - 2016 IEEE Real-Time and Embedded …, 2016 - ieeexplore.ieee.org
This work presents CArb, an arbiter for controlling accesses to the shared memory bus in
multi-core mixed criticality systems. CArb is a requirement-aware arbiter that optimally …

Integrated modular avionics (IMA) partition scheduling with conflict-free I/O for multicore avionics systems

JE Kim, MK Yoon, R Bradford… - 2014 IEEE 38th Annual …, 2014 - ieeexplore.ieee.org
The trend in the semiconductor industry toward multicore processors poses a significant
challenge to many suppliers of safety-critical real-time embedded software. Having certified …

Shedding the shackles of time-division multiplexing

F Hebbache, M Jan, F Brandner… - 2018 IEEE Real-Time …, 2018 - ieeexplore.ieee.org
Multi-core architectures pose many challenges in real-time systems, which arise from
contention between concurrent accesses to shared memory. Among the available memory …

PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems

S Hessien, M Hassan - ACM Transactions on Embedded Computing …, 2022 - dl.acm.org
Tasks in modern embedded systems such as automotive and avionics communicate among
each other using shared data towards achieving the desired functionality of the whole …