Non-volatile memory and method with non-sequential update block management

A Sinclair, S Gorobets, A Bennett… - US Patent App. 10 …, 2005 - Google Patents
In a nonvolatile memory with block management system that supports update blocks with
non-sequential logical units, an index of the logical units in a non-sequential update block is …

Non-volatile memory and method with memory planes alignment

S Gorobets, P Smith, A Bennett - US Patent App. 10/917,888, 2005 - Google Patents
(57) ABSTRACT A non-volatile memory is constituted from a Set of memory planes, each
having its own Set of read/write circuits So that the memory planes can operate in parallel …

Non-volatile memory and method with control data management

SA Gorobets, AD Bryce, AD Bennett - US Patent 8,051,257, 2011 - Google Patents
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Non-volatile memory and method with non-sequential update block management

AW Sinclair, SA Gorobets, AD Bennett… - US Patent …, 2012 - Google Patents
(US) OTHER PUBLICATIONS (*) Notice: Subject to any disclaimer, the term of this Korean
Patent Office,“Preliminary Rejection.” corresponding patent is extended or adjusted under …

Non-volatile memory and method with phased program failure handling

S Gorobets - US Patent App. 10/917,889, 2005 - Google Patents
In a memory with block management System, program failure in a block during a time-critical
memory operation is handled by continuing the programming operation in a breakout block …

Method and apparatus for managing data in a distributed buffer system

GF Pfister, RJ Recio, NC Wadia - US Patent 6,832,297, 2004 - Google Patents
A method, apparatus, and computer implemented instructions for managing a plurality of
caches of data, wherein the data processing system includes a plurality of independent …

Coherence controller for a multiprocessor system, module, and multiprocessor system with a multimodule architecture incorporating such a controller

S Lesmanne, C Bernard, P Koumou - US Patent 7,017,011, 2006 - Google Patents
(57) ABSTRACT A coherence controller is included in a module which includes a plurality of
multiprocessor units, each of which contains a main memory and processors equipped with …

Non-volatile memory and method with phased program failure handling

SA Gorobets - US Patent 7,945,759, 2011 - Google Patents
(63) Continuation of application No. 10/917,889, filed on Aug. 13, 2004, now abandoned,
which is a (57) ABSTRACT continuation-in-part of application No. 10/750,155, filed on Dec …

Mechanism for handling load lock/store conditional primitives in directory-based distributed shared memory multiprocessors

MC Mattina, C Ramey, B Jung, J Leonard - US Patent 7,620,954, 2009 - Google Patents
Each processor in a distributed shared memory system has an associated memory and a
coherence directory. The processor that controls a memory is the Home processor. Under …

Sharing pattern-based directory coherence for multicore scalability (“SPACE”)

Z Hongzhou, A Shriraman, S Dwarkadas - US Patent 9,411,733, 2016 - Google Patents
A method and directory system that recognizes and represents the subset of sharing
patterns present in an application is provided. As used herein, the term sharing pattern …