Comprehensive Study of Low-Power SRAM Design Topologies

A Srivastav, SK Tripathi, U Tiwari… - Recent Advances in …, 2024 - benthamdirect.com
The need for low power in portable and smart devices is the demand to be fulfilled for
sustaining the semiconductor industry. Static Random Access Memory (SRAM) is the main …

[PDF][PDF] Estimation of power and delay in CMOS circuits using LCT

AP Kumar, B Aditya, G Sony, C Prasanna… - Indones. J. Electr. Eng …, 2019 - academia.edu
With a rapid growth in semiconductor Industry, complex applications are being implemented
using small size chips, with the use of Complementary Metal Oxide Semi-Conductors …

Low Power High Stability SRAM Cell with Combined Effect of Sleep-Stack and Diode Gated Technique

KB Ray, BS Patro - 2018 International Conference on Applied …, 2018 - ieeexplore.ieee.org
In this work, Static Random Access Memory (SRAM) is designed on 0.18 micron by using
CADENCE virtuoso tools. It focuses on the power consumption and leakage power …

[PDF][PDF] Estimation of Power and Delay in CMOS Circuits using Leakage Control Transistor

AP Kumar, B Aditya, G Sony, C Prasanna… - Carpathian Journal of …, 2018 - sciendo.com
With a rapid growth in semiconductor Industry, complex applications are being implemented
using small size chips, with the use of Complementary Metal Oxide Semi-Conductors …

IMPLEMENTATION OF POWER REDUCTION IN CMOS CIRCUITS.

DS Kumar, K RAJASEKHAR - I-Manager's Journal on …, 2019 - search.ebscohost.com
In recent trends, the industry and most researchers are focusing on the scale down of CMOS
technologies to improve the speed and leakage power reduction in the circuits. These …

[PDF][PDF] Leakage Power Minimization in ST-SRAM Cell Using Adaptive Reverse Body Bias Technique

K Ray, BS Patro - 2018 - researchgate.net
Nowadays, we all are using battery operated devices and the devices require extremely low
power to maximize the lifetime of the battery. Maximum devices are storing their data in …

[引用][C] IMPLEMENTATION OF POWER REDUCTION IN CMOS CIRCUITS

[引用][C] A Comprehensive Review on Applications of Don't Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems

S Mitra, D Das - Indonesian Journal of Electrical Engineering and …, 2018