[图书][B] System-on-a-chip: Design and Test

R Rajsuman - 2000 - ieeexplore.ieee.org
Starting with a basic overview of system-on-a-chip (SoC), including definitions of related
terms, this new book helps you understand SoC design challenges, and the latest design …

Recent developments on DAC modelling, testing and standardization

E Balestrieri, P Daponte, S Rapuano - Measurement, 2006 - Elsevier
In the last years the technology improvements of Digital-to-Analog Converters (DACs) has
extended the use of digital techniques in a multitude of applications. Consequently, there is …

An on chip ADC test structure

YC Wen, KJ Lee - Proceedings of the conference on Design, automation …, 2000 - dl.acm.org
In this paper, a new built-in self-test structure to test the static specifications of analog to
digital converters (ADCs) is presented. A ramp signal generated by an integrator serves as a …

ANOVA-based approach for DAC diagnostics

M D'Arco, A Liccardo… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
In order to assess the performance of digital-to-analog converters (DAC) the attention is
generally focused on the integral nonlinearity INL. Useful diagnostic tools to detect the …

Transition-code based linearity test method for pipelined ADCs with digital error correction

JF Lin, SJ Chang, TC Kung, HW Ting… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
A transition-code based method is proposed to reduce the linearity testing time of pipelined
analog-to-digital converters (ADCs). By employing specific architecture-dependent rules …

A high precision ramp generator for low cost ADC test

WT Lee, YZ Liao, JC Hsu, YS Hwang… - 2008 9th International …, 2008 - ieeexplore.ieee.org
In this paper, we have proposed a new high precision ramp waveform generator for low cost
ADC test. With proposed test method combined with histogram analysis, an ADC can be …

A Design-for-Digital-Testability Circuit Structure for - Modulators

HC Hong - IEEE Transactions on Very Large Scale Integration …, 2007 - ieeexplore.ieee.org
A design-for-digital-testability (DfDT) switched-capacitor circuit structure for testing Sigma-
Delta modulators with digital stimuli is presented to reduce the overall testing cost. In the test …

[PDF][PDF] A sigma-delta modulation based BIST scheme for mixed-signal circuits

JL Huang, KT Cheng - Proceedings of the 2000 Asia And South Pacific …, 2000 - dl.acm.org
In this work, we present the analysis of a built-in self-test (BIST) scheme for mixed-signal
circuits that is intended to provide on-chip stimulus generation and response analysis …

Practical considerations in applying/spl Sigma/-/spl Delta/modulation-based analog BIST to sampled-data systems

HC Hong, JL Huang, KT Cheng… - IEEE Transactions on …, 2003 - ieeexplore.ieee.org
The analog built-in self-test (BIST) scheme, with stimulus generation and response
extraction based on the/spl Sigma/-/spl Delta/modulation, is proven to be quite effective for …

A Fully Integrated Built-In Self-Test ADC Based on the Modified Controlled Sine-Wave Fitting Procedure

HC Hong, FY Su, SF Hung - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
This paper demonstrates the first fully integrated built-in self-test (BIST) Σ-Δ analog-to-digital
converter (ADC) chip to the best of our knowledge. The ADC under test (AUT) comprises a …