Low power image processing applications on FPGAs using dynamic voltage scaling and partial reconfiguration

A Podlubne, J Haase, L Kalms, G Akgün… - 2018 Conference on …, 2018 - ieeexplore.ieee.org
The TULIPP project aims to facilitate the development of embedded image processing
systems with real-time and low-power constraints. In this paper, several adaptive dynamic …

Holistic IJTAG-based external and internal fault monitoring in uavs

F Ahmed, M Jenihhin - 2023 IEEE 24th Latin American Test …, 2023 - ieeexplore.ieee.org
Cyber-Physical Systems (CPSs), such as Unmanned Aerial Vehicles (UAVs), use System-on-
Chip (SoC) based computing platforms to perform multiple complex tasks in safety-critical …

An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation

G Cano-Quiveu, P Ruiz-De-Clavijo-Vazquez… - IEEE …, 2021 - ieeexplore.ieee.org
This paper introduces a design and on-chip verification framework for IPCores in FPGA
platforms. The methodology of the proposed framework is based on the development of a …

An intrusive dynamic reconfigurable cycle-accurate debugging system for embedded processors

HH Khan, A Kamal, D Goehringer - … , ARC 2018, Santorini, Greece, May 2 …, 2018 - Springer
This paper presents a dynamic partial reconfigurable debugging system for embedded
processors based upon a device start and stop (DSAS) approach [1]. Using this approach, a …

Time-multiplexed 10gbps ethernet-based integrated logic analyzer for fpgas

S Popa, M Ivanovici, RM Coliban - … international symposium on …, 2020 - ieeexplore.ieee.org
We designed a time-multiplexed high-speed integrated logic analyzer (ILA) probing system
for FPGA device technology, which is currently under implementation. The high-speed …

Intrusive FPGA-in-the-loop debugging using a rule-based inference system

A Podlubne, D Göhringer - Microprocessors and Microsystems, 2019 - Elsevier
This paper presents an intrusive FPGA-in-the-loop (FIL) debugging methodology by using a
rule-based inference system. In this methodology, a cycle-accurate lossless debugging …

Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks

HH Khan, A Podlubne, G Akgün… - … . Architectures, Tools, and …, 2020 - Springer
This research work presents a methodology for debugging embedded designs by using
recurrent neural networks. In this methodology, a cycle-accurate lossless debugging system …

Cycle-Accurate Debugging of Multi-clock Reconfigurable Systems

G Akgün, A Podlubne, F Wegener… - 2019 International …, 2019 - ieeexplore.ieee.org
This paper presents a cycle accurate intrusive debugging methodology for embedded
designs having multiple-clock domains. In this methodology, a cycle-accurate lossless …

Continuous live-tracing as debugging approach on FPGAs

C Blochwitz, R Klink, JM Joseph… - … Computing and FPGAs …, 2017 - ieeexplore.ieee.org
This work presents a new approach for monitoring and debugging RTL logic on FPGAs-Live-
Tracing-Logic. The design combines the two most common approaches for debugging RTL …

FPGA Debugging with MATLAB Using a Rule-Based Inference System

HUH Khan, D Göhringer - … 13th International Symposium, ARC 2017, Delft …, 2017 - Springer
This paper presents an FPGA debugging methodology using a rule based inference system.
Using this approach, the design stops a device under test (DUT), saves the data to external …