SwiftTron: An efficient hardware accelerator for quantized transformers

A Marchisio, D Dura, M Capra… - … Joint Conference on …, 2023 - ieeexplore.ieee.org
Transformers' compute-intensive operations pose enormous challenges for their deployment
in resource-constrained EdgeAI/tiny ML devices. As an established neural network …

VLSI implementation of anti‐notch lattice structure for identification of exon regions in Eukaryotic genes

V Pathak, SJ Nanda, AM Joshi… - IET Computers & Digital …, 2020 - Wiley Online Library
In a Eukaryotic gene, identification of exon regions is crucial for protein formation. The
periodic‐3 property of exon regions has been used for its identification. An anti‐notch infinite …

An area-delay efficient single-precision floating-point multiplier for VLSI systems

SK Patel, SK Singhal - Microprocessors and Microsystems, 2023 - Elsevier
The floating-point multiplier (FPM) is the most commonly used component in various image
and signal processing applications. An area-delay efficient FPM design could be helpful for …

FPGA implementation of high‐speed tunable IIR band pass notch filter for identification of hot‐spots in protein

V Pathak, SJ Nanda, AM Joshi… - International Journal of …, 2021 - Wiley Online Library
Localization of hot spots in a protein sequence is an important problem for understanding
complex 3D structure of amino acid sequence (due to which biological functionality of …

FPGA implementation of IIR notch and anti-notch filters with an application to localization of protein hot-spots

AK Yadav, BC Nagar, G Pradhan - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
In this paper, high-speed second-order infinite impulse response (IIR) notch filter (NF) and
anti-notch filter (ANF) are designed and realized on hardware. The improvement in speed of …

Time domain numerical simulation for transient waves on reconfigurable coprocessor platform

C He, W Zhao, M Lu - 13th Annual IEEE Symposium on Field …, 2005 - ieeexplore.ieee.org
A successful application-oriented reconfigurable coprocessor design requires not only a
powerful FPGA-based computing engine along with suitable hardware architecture, but also …

Identification of characteristics frequency and hot-spots in protein sequence of COVID-19 disease

V Pathak, SJ Nanda, AM Joshi, SS Sahu - Biomedical Signal Processing …, 2022 - Elsevier
COVID-19 has threatened the whole world since December 2019 and has also infected
millions of people around the globe. It has been transmitted through the SARS CoV-2 virus …

Parallel processor design and implementation for molecular dynamics simulations on a FPGA-based supercomputer

S Kasap, K Benkrid - Journal of Computers, 2012 - pureportal.coventry.ac.uk
The design and implementation of an FPGA core that parallelises all the necessary
operations to compute the non-bonded interactions in a MD simulation with the purpose of …

Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier

X Jiang, P Xiao, M Qiu, G Wang - Microprocessors and Microsystems, 2013 - Elsevier
High pipeline depth architecture with pipeline stage more than five is rarely adopted in
existing multipliers for real world applications. In this paper, a field programmable gate array …

Systems and methods for generating code from executable models with floating point data

KK Kintali, S Dutta, AS Krishnamoorthi… - US Patent …, 2018 - Google Patents
Abstract Systems and methods generate code from an executable model. The model may
operate on variables having floating point data types. The systems and methods may …