Prospects and applications of photonic neural networks

C Huang, VJ Sorger, M Miscuglio… - … in Physics: X, 2022 - Taylor & Francis
Neural networks have enabled applications in artificial intelligence through machine
learning, and neuromorphic computing. Software implementations of neural networks on …

A survey of ReRAM-based architectures for processing-in-memory and neural networks

S Mittal - Machine learning and knowledge extraction, 2018 - mdpi.com
As data movement operations and power-budget become key bottlenecks in the design of
computing systems, the interest in unconventional approaches such as processing-in …

Analogue signal and image processing with large memristor crossbars

C Li, M Hu, Y Li, H Jiang, N Ge, E Montgomery… - Nature …, 2018 - nature.com
Memristor crossbars offer reconfigurable non-volatile resistance states and could remove
the speed and energy efficiency bottleneck in vector-matrix multiplication, a core computing …

Dot-product engine for neuromorphic computing: Programming 1T1M crossbar to accelerate matrix-vector multiplication

M Hu, JP Strachan, Z Li, EM Grafals, N Davila… - Proceedings of the 53rd …, 2016 - dl.acm.org
Vector-matrix multiplication dominates the computation time and energy for many workloads,
particularly neural network algorithms and linear transforms (eg, the Discrete Fourier …

Low-power linear computation using nonlinear ferroelectric tunnel junction memristors

R Berdan, T Marukame, K Ota, M Yamaguchi… - Nature …, 2020 - nature.com
Analogue in-memory computing using memristors could alleviate the performance
constraints imposed by digital von Neumann systems in data-intensive tasks. Conventional …

Comprehensive model of electron conduction in oxide-based memristive devices

C Funck, S Menzel - ACS Applied electronic materials, 2021 - ACS Publications
Memristive devices are two-terminal devices that can change their resistance state upon
application of appropriate voltage stimuli. The resistance can be tuned over a wide …

Solving matrix equations in one step with cross-point resistive arrays

Z Sun, G Pedretti, E Ambrosi, A Bricalli… - Proceedings of the …, 2019 - National Acad Sciences
Conventional digital computers can execute advanced operations by a sequence of
elementary Boolean functions of 2 or more bits. As a result, complicated tasks such as …

Sparse reram engine: Joint exploration of activation and weight sparsity in compressed neural networks

TH Yang, HY Cheng, CL Yang, IC Tseng… - Proceedings of the 46th …, 2019 - dl.acm.org
Exploiting model sparsity to reduce ineffectual computation is a commonly used approach to
achieve energy efficiency for DNN inference accelerators. However, due to the tightly …

Mitigating effects of non-ideal synaptic device characteristics for on-chip learning

PY Chen, B Lin, IT Wang, TH Hou, J Ye… - 2015 IEEE/ACM …, 2015 - ieeexplore.ieee.org
The cross-point array architecture with resistive synaptic devices has been proposed for on-
chip implementation of weighted sum and weight update in the training process of learning …

A full-stack view of probabilistic computing with p-bits: devices, architectures, and algorithms

S Chowdhury, A Grimaldi, NA Aadit… - IEEE Journal on …, 2023 - ieeexplore.ieee.org
The transistor celebrated its 75th birthday in 2022. The continued scaling of the transistor
defined by Moore's law continues, albeit at a slower pace. Meanwhile, computing demands …