4K real-time HEVC decoder on an FPGA
M Abeydeera, M Karunaratne… - … on Circuits and …, 2015 - ieeexplore.ieee.org
With the popularization of a quad high-definition/4K video being dependent on the
availability of real-time High Efficiency Video Coding (HEVC) decoders, hardware …
availability of real-time High Efficiency Video Coding (HEVC) decoders, hardware …
The vlsi architecture of a highly efficient deblocking filter for hevc systems
PK Hsu, CA Shen - IEEE Transactions on Circuits and Systems …, 2016 - ieeexplore.ieee.org
This paper presents the VLSI architecture and hardware implementation of a highly efficient
deblocking filter (DBF) for High Efficiency Video Coding systems. In order to reduce the …
deblocking filter (DBF) for High Efficiency Video Coding systems. In order to reduce the …
FPGA implementation of a full HD real-time HEVC main profile decoder
D Engelhardt, J Moller, J Hahlbeck… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
High Efficiency Video Coding (HEVC) is the newest video coding standard approved by the
ISO/IEC and ITU-T in January 2013. By providing a video coding efficiency gain up to 50 …
ISO/IEC and ITU-T in January 2013. By providing a video coding efficiency gain up to 50 …
An 8K H. 265/HEVC video decoder chip with a new system pipeline design
8K ultra-HD is being promoted as the next-generation video specification. While the High
Efficiency Video Coding (HEVC) standard greatly enhances the feasibility of 8K with a …
Efficiency Video Coding (HEVC) standard greatly enhances the feasibility of 8K with a …
A dual-clock VLSI design of H. 265 sample adaptive offset estimation for 8k ultra-HD TV encoding
Sample adaptive offset (SAO) is a newly introduced in-loop filtering component in H.
265/High Efficiency Video Coding (HEVC). While SAO contributes to a notable coding …
265/High Efficiency Video Coding (HEVC). While SAO contributes to a notable coding …
Sample adaptive offset (SAO) filtering in video coding
H04N 9/89(2014.01) Frank D. Cimino H04N 9/14(2014.01) H04N 9/82(2014.01)(57)
ABSTRACT H04N 9/436(2014.01) A method for sample adaptive offset (SAO) filtering of …
ABSTRACT H04N 9/436(2014.01) A method for sample adaptive offset (SAO) filtering of …
Fast SAO estimation algorithm and its VLSI architecture
SAO estimation is the process of determining SAO parameters in video encoding. There are
two difficulties for VLSI implementation of SAO estimation. The first is that there are huge …
two difficulties for VLSI implementation of SAO estimation. The first is that there are huge …
High throughput VLSI architecture for HEVC SAO encoding for ultra HDTV
This paper presents a high performance, silicon area efficient, and software configurable
hardware architecture for sample adaptive offset (SAO) encoding. The paper proposes a …
hardware architecture for sample adaptive offset (SAO) encoding. The paper proposes a …
Programmable low-power multicore coprocessor architecture for HEVC/H. 265 in-loop filtering
I Hautala, J Boutellier, J Hannuksela… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
The High Efficiency Video Coding (HEVC) in-loop filtering is designed to reduce coding
artifacts caused by image transforms and quantizations. HEVC in-loop filtering is divided to …
artifacts caused by image transforms and quantizations. HEVC in-loop filtering is divided to …
A high-throughput HEVC deblocking filter VLSI architecture for 8k× 4k application
As the next generation of video coding standard, High Efficiency Video Coding (HEVC) aims
to reduce 50% bit rates in comparison with previous video coding standards. In order to …
to reduce 50% bit rates in comparison with previous video coding standards. In order to …