The objective of IFRA, Instruction Footprint Recording and Analysis, is to overcome the
challenges associated with a very expensive step in post-silicon validation of processors …

This paper describes the implementation of the IBM POWER6™ microprocessor, a two-way
simultaneous multithreaded (SMT) dual-core chip whose key features include binary …

Energy-efficient computation is critical if we are going to continue to scale performance in
power-limited systems. For floating-point applications that have large amounts of data …

The IBM POWER6™ microprocessor core includes two accelerators for increasing
performance of specific workloads. The vector multimedia extension (VMX) provides a vector …

A novel data prefetching method--access map pattern matching (AMPM)--that uses" memory
access map" is proposed. The AMPM prefetching concentrate hardware resources on …

Hardware support for floating-point (FP) arithmetic is a mandatory feature of modern
microprocessor design. Although division and square root are relatively infrequent …

A microprocessor is configured for unchained and chained modes of split execution of a
fused compound arithmetic operation. In both modes of split execution, a first execution unit …

In this paper, a new leading-zero counter (or detector) is presented. New boolean relations
for the bits of the leading-zero count are derived that allow their computation to be performed …

When operating on a rapidly increasing amount of data, business analytics applications
become sensitive to rounding errors, and profit from the higher stability and faster …

In this work we present a new 64-bit floating point Fused Multiply Add (FMA) unit that can
perform both binary and decimal addition, multiplication, and fused-multiply-add operations …