Recent directions in netlist partitioning: A survey

CJ Alpert, AB Kahng - Integration, 1995 - Elsevier
This survey describes research directions in netlist partitioning during the past two decades
in terms of both problem formulations and solution approaches. We discuss the traditional …

Metaheuristics: A bibliography

IH Osman, G Laporte - Annals of Operations research, 1996 - Springer
Metaheuristics are the most exciting development in approximate optimization techniques of
the last two decades. They have had widespread successes in attacking a variety of difficult …

[图书][B] Architecture and CAD for deep-submicron FPGAs

V Betz, J Rose, A Marquardt - 2012 - books.google.com
Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become
one of the most popular implementation media for digital circuits and have grown into a $2 …

[图书][B] Handbook of approximation algorithms and metaheuristics

TF Gonzalez - 2007 - taylorfrancis.com
Delineating the tremendous growth in this area, the Handbook of Approximation Algorithms
and Metaheuristics covers fundamental, theoretical topics as well as advanced, practical …

[图书][B] Electronic design automation: synthesis, verification, and test

LT Wang, YW Chang, KTT Cheng - 2009 - books.google.com
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …

Genetic algorithm and graph partitioning

TN Bui, BR Moon - IEEE Transactions on computers, 1996 - ieeexplore.ieee.org
Hybrid genetic algorithms (GAs) for the graph partitioning problem are described. The
algorithms include a fast local improvement heuristic. One of the novel features of these …

Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors

RL Maziasz, M Guruswamy, S Raman - US Patent 6,209,123, 2001 - Google Patents
(57) ABSTRACT A method of automatically placing transistors of a folded transistor circuit for
Synthesizing rows of transistors in a Semiconductor layout (172). First, an initial placement …

Design hierarchy-based placement

M Igusa, HC Chen, SP Chao, WJ Dai… - US Patent …, 2001 - Google Patents
1998-01-09 Assigned to RELAY DESIGN AUTOMATION INCORPORATED reassignment
RELAY DESIGN AUTOMATION INCORPORATED ASSIGNMENT OF ASSIGNORS …

Generic global placement and floorplanning

H Eisenmann, FM Johannes - Proceedings of the 35th annual Design …, 1998 - dl.acm.org
We present a new force directed method for global placement. Besides the well-known wire
length dependent forces we use additional forces to reduce cell overlaps and to consider the …

[PDF][PDF] Fast template placement for reconfigurable computing systems

K Bazargan, R Kastner, M Sarrafzadeh - IEEE design & Test of …, 2000 - Citeseer
The advances in the programmable hardware have lead to new architectures, where the
hardware can be dynamically adapted to the application to gain better performance. One of …