S Tanwir, S Prabhu, M Hsiao… - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
Diagnosis of each failed part requires the failed data captured on the test equipment. However, due to memory limitations on the tester, one often cannot store all the failed data …
Y Higami, Y Kurose, S Ohno… - 2009 International …, 2009 - ieeexplore.ieee.org
This paper presents a diagnostic test generation method for transition faults. As two consecutive vectors application mechanism, launch on capture test is considered. The …
Y Zhang, VD Agrawal - 2011 IEEE 29th International …, 2011 - ieeexplore.ieee.org
To distinguish between a pair of transition faults, we need to find a test vector pair (LOC or LOS type) that produces different output responses for the two faults. By adding a few logic …
Y Zhang, VD Agrawal - 2010 11th Latin American Test …, 2010 - ieeexplore.ieee.org
In diagnostic testing faults detectable by test vectors are partitioned into groups. This partitioning is such that a fault is distinguishable from faults in all other groups, but is …
S Chillarige, A Chhabra, A Malik… - 2018 IEEE …, 2018 - ieeexplore.ieee.org
Recent innovations in Test Compression are enabling implementation of very high compression ratios. This paper analyzes the impact of high compression on resolution and …
Y Zhang, B Zhang, VD Agrawal - Journal of Electronic Testing, 2014 - Springer
By adding a few logic gates and one or two modeling flip-flops to the circuit under test (CUT), we create a detection or diagnostic automatic test pattern generation (ATPG) model of …
In VLSI testing we need Automatic Test Pattern Generator (ATPG) to get input test vectors for Circuit Under Test (CUT). Generated test sets are usually compacted to save test time which …
B Seshadri, X Yu… - 24th IEEE VLSI Test …, 2006 - ieeexplore.ieee.org
We propose techniques to speed up diagnostic fault simulation for circuits without full-scan which may need multi-cycle tests. First, we introduce the concept of z-sets for circuits without …