A 40 nm dual-width standard cell library for near/sub-threshold operation

J Zhou, S Jayapal, B Busze, L Huang… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
Near/sub-threshold operation is promising to achieve energy minimization when high
performance is not required. The device sizing in sub-threshold region is different from super …

A 457 nW near-threshold cognitive multi-functional ECG processor for long-term cardiac monitoring

X Liu, J Zhou, Y Yang, B Wang, J Lan… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
A low-power multi-functional electrocardiogram (ECG) signal processor is presented in this
paper. To enable long-term monitoring, several architecture-level power saving techniques …

High performance energy efficient radiation hardened latch for low voltage applications

CI Kumar, A Bulusu - Integration, 2019 - Elsevier
Energy efficiency is considered to be the most critical design parameter for IoT and other
ultra low power applications. However, energy efficient circuits show a lesser immunity …

Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS

AA Vatanjou, T Ytterdal, S Aunet - 2015 6th Asia Symposium on …, 2015 - ieeexplore.ieee.org
This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (“RCA”),
demonstrating functionality for a supply voltage (“V dd”) down to 84 mV. The low V dd might …

High-sensitivity ultra-low-power electrode resistance monitoring circuit for cardiac pacemakers

J Xu, Z Yu, Y Wang, R Zhang, H Zhang - Analog Integrated Circuits and …, 2021 - Springer
An electrode resistance monitoring circuit utilizing current comparison is proposed and
demonstrated for implantable cardiac pacemakers. The resistance detection circuit …

Digital circuit design for robust ultra-low-power cell library using optimum fingers

R Liao, C Hutchens - 2012 IEEE 55th International Midwest …, 2012 - ieeexplore.ieee.org
This paper presents a design methodology considering both INWE (Inverse-Narrow-Width-
Effect) and RSCE (Reverse-Short-Channel-Effect) by sizing transistor's width and length …

Hierarchical variability-aware compact models of 20nm bulk CMOS

X Wang, D Reid, L Wang, A Burenkov… - … on Simulation of …, 2015 - ieeexplore.ieee.org
This paper presents a hierarchical variability-aware compact model methodology based on
a comprehensive simulation study of global process variation and local statistical variability …

Measurement forecast of anomalous threshold voltages in BCD LV submicron n-MOSFETs with two artificial intelligence methods

SL Chen, DY Shu - Measurement, 2017 - Elsevier
In this study, two intelligent methodologies were used to estimate the anomalous threshold-
voltage (V th) measured behaviors in sub-micrometer Bipolar-CMOS-DMOS (BCD) low …

A 2μW digital baseband core for wireless Micro-Neural-Interface in 0.18 μm CMOS

R Liao, C Hutchens… - 2013 IEEE International …, 2013 - ieeexplore.ieee.org
This paper presents the design of a low power digital baseband core with a custom-tailored
protocol for wirelessly powered Micro-Neural-Interface (MNI) system on a chip (SoC) to be …

An energy-efficient variation aware self-correcting latch

CI Kumar, AK Sharma, R Partap, A Bulusu - Microelectronics Journal, 2019 - Elsevier
Power dissipation is a prime concern in sub-nanometer VLSI regime and, therefore,
operation at near/sub-threshold regime has gained importance. However, though energy …